Field-Programmable Gate Array

CPLD Development Boards

MAX II EPM240 CPLD Development Board

I got the MAX II EPM240 minimal development board in an electronics job lot and was my first CPLD development board but although I had previous experience with FPGA boards, I found the CPLD board to have a fault, which I'll get into shortly. The board appears to be from 2009 and measures just 5cm x 7cm, and features an EPM240T100C5 CPLD and a standard on-board JTAG interface, requiring a USB Blaster or similar device to program it. The board also contains a 50MHZ crystal oscillator, single user LED, 5V power supply socket and switch (a 3.3V on-board regulator reduces the voltage for the CPLD), and the various I/O are accessible through a number of header pins.

You can view the board and various links that will help in developing for the board at:

https://artofcircuits.com/product/altera-max-ii-epm240-cpld-development-board

The links are toward the bottom of the page. Note that there are two separate schematics that are linked to but both are required.

FPGA Development Boards

A relatively cheap and straightforward means to try out different FPGAs is by using an FPGA development board which contains an FPGA, power circuitry, I/O connectors and possibly I/O devices, like switches, LEDs, and so on. The board will likely also have some kind of interface to a PC for configuration and debugging, which may either be a USB port if the board contains an on-board programmer (such as a USB Blaster) or some other connector, such as JTAG, for connection to an external programmer/debugger device to do the configuration. An FPGA board that uses an external configuration device has the advantage that the board can be smaller than if the device was on-board but it is very convenient to have such a configuration circuit built-in. Of course if you buy such a development board that uses an external configuration device ensure that it is included or you'll have to source one elsewhere.

When looking for an FPGA development board one important factor of course is the FPGA itself and although there are a lot of specs for an FPGA you should at least consider the FPGA's clock speed, the memory blocks it has, how many logic elements (LEs) the FPGA has as well as how many I/O connections provided by the FPGA and how many are available on the development board for your own use as general purpose I/O. FPGAs typically only have digital I/O so one thing you may want from the development board is some analogue inputs (via an ADC converter) and possibly analogue outputs (using a DAC) which is handy for VGA, for example. It is also useful that the development board has on-board RAM that can be utilised by the FPGA as complex designs may need more RAM than the FPGA has itself.

Software is required to create designs for FPGAs, with Quartus being an example for Altera FPGAs, which comes in both free and paid for versions, FPGA designs are downloaded to the development board but are lost when power is removed. This allows for rapid iteration and testing and once you are happy with the design you can write the design to some form of non-volatile memory (e.g. flash) on the development board. Depending on the particular development board you have there will be a specific way to write the configuration to the non-volatile memory memory.

In this section we will now look at some FPGA development boards that you can purchase, ranging from older FPGA boards to more recent ones, going over their features and my experiences with them. You may expect that the older boards would prove to be tricky to get working, and indeed that can be the case due to having to get software designed for older computers to work on newer ones, but even the newer boards have their quirks. Fortunately, as well as the information presented on my site there is also a lot of other help online, including video tutorials, but I would advise to do your research first before investing in any FPGA development system.

Arrow Electronics FPGA Boards

Please go to Arrow Electronics FPGA Boards.

Cyclone II Development Board

For my first adventure into FPGA's I bought a Cyclone II development board and a USB blaster which is used to program the FPGA and the flash memory that stores the configuration; changes to the FPGA are lost when power is removed and at power-up the configuration is re-loaded from flash memory. The development board features an Altera EP2C5T144C8 FPGA which has 89 I/O (most available on the board), 4608 logic elements and runs at a maximum frequency of 250MHz. The board has 3 LED's and a switch already connected to the FPGA I/O (so they are good for test designs), as well as a power LED. There are two sockets for the programmer, one for Active Serial Programming to update the flash configuration and another socket for JTAG which is used to download designs to the FPGA. There are four lots of headers for accessing the other I/O.

As mentioned there is a flash memory chip for permanently storing your design which is the EPCS4S18 4Mbit chip which can be programmed at least 100,000 times. There is a default configuration stored in the flash memory which flashes the 3 LED's.

The development board is powered from a 5V power supply using the on-board socket or you can solder your own connector or wires to the provided connections on the PCB. I used an unregulated 4.5V DC 300mA supply since the DC input goes to a voltage regulator so when connected to the development board it was the right voltage.

To develop designs and download them to the FPGA you can use Quartus II software version 13.0 sp1 (newer versions of the software don't support Cyclone II) available for download from https://www.altera.com/ which has a free version which has less features than the paid for version. You will need to download the main software (1.5GB) and then the device software for the FPGA (~500MB). After installing the main software you need to open it and then go to Tools->Install devices... and follow the instructions.

The Altera USB blaster came with a small instruction manual mainly in Chinese, so that was no help. When the USB blaster is connected to the PC Windows will fail when trying to install the driver. So go to the device manager and right-click on the USB blaster device and select Update driver. Select Browse for driver software and go to where the Quartus software was installed and select the drivers\usb-blaster directory. For me the full path was:

C:\altera\13.0sp1\quartus\drivers\usb-blaster

Click next and then click close when the software has been installed.

For more info see:

https://www.altera.com/support/support-resources/download/drivers/usb-blaster/dri-usb-blaster-vista.html

The next thing to do is set up Quartus II software to use the USB blaster. Open Quartus II and go to Tools->Programmer and click Hardware Setup. You should see the USB blaster listed; double-click it and click Close.

Full instructions are at:

https://www.altera.com/support/support-resources/download/drivers/dri-quartus.html

For a simple design, the USB blaster is very fast to program (about 2 seconds). Storing the design in flash memory, however, is somewhat slower.

For my first design, I followed a tutorial at:

https://www.altera.com/en_US/pdfs/literature/tt/tt_my_first_fpga.pdf

Adapting it as necessary for my development board (the tutorial is for newer FPGA's). The aim of the tutorial is to teach the basics of FPGA design and the end result is that a number of LED's turn on and off in a binary pattern. Because, however, the LED's are active low the sequence is inverted; most likely the on-board LED's are connected to the positive supply rail to provide more current.

For my second design I built on the first tutorial to turn three LED's on and off in turn. I found there were a number of emulated 74' series logic components so I was able to use a 7490 to do the counting. I did, however, have a lot of trouble with using the emulated 74' chips because if you don't connect them right, when you go to Start Analysis & Synthesis Quartus will complain that the circuit won't do anything (which is right) but then infer the main clock is pointless (which again, is true).

Next, I did another adaptation which counted from 0 to 9 but outputted the numbers to a 7-segment LED display. This was a good test in connecting external components to the development board. Note that these simple designs used just 1% of the total logic elements available in the FPGA chip.

Some other cool features of the FPGA is the ability to set the I/O standard to use for each I/O connection, which can be found under Assignments->Pin Planner... In the same window you can set for each I/O the current strength from as little as 4mA to 24mA and higher.

DE1-SoC Development Board

Please see The DE1-SoC.

Digilent Nexys 3 Development Board

Please go to Digilent Nexys 3.

Olimex ICE40HX1K-EVB Development Board

I took a chance in 2023 with the open source ICE40HX1K-EVB FPGA board from Olimex Ltd., which set me back £13.44 from Mouser, and is for evaluating the iCE40HX1K FPGA.

Here is a page detailing the announcement of the product:

https://olimex.wordpress.com/2016/05/06/ice40hx1k-evb-open-source-hardware-fpga-board-designed-with-kicad-and-working-with-icestorm-foss-toolchain-first-prototypes-are-ready-and-run/

The page is dated 6th May 2016, so the board seems to be from that year.

Before buying, I did look online briefly to see how it was programmed and even though it doesn't use the JTAG standard I was used to I found a tutorial online involving a Raspberry Pi as the programmer. However, when I got the board and tried to get it to work I had to go though several tutorials before successfully programming it.

As is typical with FPGA boards, you can either configure the FPGA directly (the configuration is lost when power is removed) or you can write to the flash memory so that the design persists power loss. The first tutorials I followed (which I failed to get working) targeted the flash directly but I was able to directly configure the FPGA thanks to a different guide but before going into how I got the board working let's look into more detail about its specification.

The board measures just 50 x 50mm, runs off 5V through the barrel jack connector, but does have the option to be powered via the 3.3V (normally open) connection on the PGM (program) connector, which requires a soldered connection to be made. Only 3.3V devices can be used to program the FPGA board, any higher voltage will likely damage it, so if you plan to use a board with 5V I/O for programming then you must use level shifters to convert 5V to 3.3V.

The ICE40HX1K-EVB uses the iCE40HX1K-VQ100 FPGA (1280 Logic cells and 64K embedded RAM bits), paired with 512KB SRAM (256Kx16bit 10ns) and 2MB Serial Flash. There is a red power led (PWR1), two user status red LEDs (LED1/IOB_41 and LED2/IOR_52), a programming (configuration) successful status green LED (CDONE1), two user buttons (BUT1/IOB_42_CBSEL0 and BUT2/IOB_43_CBSEL1), and a reset button (RESET1/CRESET_B). There is a 34-pin (17 x 2) IDC connector with male pins, which carries all unused I/O signals from the FPGA, and is conveniently the same type used by most PC 3.5" floppy drives, considering there is an abundance of those cables for sale.

I found that my ICE40HX1K-EVB already had an FPGA configuration programmed into the flash; when you power the board, pressing BUT2 causes LED1 to light and pressing BUT1 lights LED2 (a little odd to have it that way round but it proved useful later on). Although I only found out about the default configuration through trying the buttons myself, I came across what appeared to be the source code at:

https://olimex.wordpress.com/2016/07/12/hello-world-with-verilog-on-ice40hx1k-evb-with-open-source-tool-icestorm/

This revealed that you can press BUT1 and BUT2 together to switch between two modes. The second mode causes one led to turn on and off, then the second, and repeat. The author claims that the LEDs blink by default - rather than respond to the switches - before switching modes and that BUT1 lights LED1, but perhaps they changed the default mode at some point. As a matter of interest, I measured that the current drawn by the board when powered by 5V is around 13mA when the users LEDs are off, rising to ~14mA when LED1 and LED2 are both on.

To generate the configuration (bitmap) file for the FPGA I followed this tutorial which involves using iCEcube2 software:

https://github.com/OLIMEX/iCE40HX1K-EVB/blob/master/windows/icecube2/HowTo%20iCE40%20under%20Windows.pdf

I ended up with the bitmap file top_bitmap.bin, however, in step 4 where it details how to program the FPGA I wasn't successful using their method. I tried using an Arduino Mega with level shifters but I couldn't get it to program the FPGA no matter how many times I tried or how long I waited. Fortunately, I found a tutorial that worked for me, which lets you program the FPGA directly (rather than the flash). This is the site that I found:

https://hackaday.io/page/6119-programming-an-ice40hx4k-with-an-arduino-and-python

The author used a SparkFun SAMD21 Mini Breakout to program an iCE40HX4K (similar to a iCE40HX1K) and fortunately I happened to have my own SAMD21-type board with the same ARM chip, a Seeeduino Xiao or Seeed Studio XIAO as it's also known as, which I bought by chance at the same time as the ICE40HX1K-EVB. The nice thing about these types of boards is that the I/O operates at 3.3V so there is no need to use level shifters with the ICE40 board.

I copied the Arduino sketch from the site linked above but when tried to compile it I got the error:

'SerialUSB' was not declared in this scope

The fix is to put:

#define SerialUSB Serial

Along with the other #define statements at the start of the sketch.

The other issue I came across is that in the Arduino sketch 'RESET_PIN' is declared as digital pin 10 but on the Seeeduino Xiao it is used as MOSI for SPI so I changed it to 7. The Arduino sketch was then transferred to the Xiao.

Note that in the author's circuit, the FPGA'S SS pin (U1A/IOB_108_SS), is always held low (to GND) so I did the same, taking the ICE40's programming pin 10 (SS_B) to GND.

Then on to the Python side, I used Python 3.10.9, and copied in the Python code that follows the Arduino sketch. Since I'm using Windows I had to change this line:

ser = serial.Serial('/dev/ttyACM0', 115200, timeout=1)

To:

ser = serial.Serial('COM6', 115200, timeout=1)

Because '/dev/ttyACM0' is relevant for Linux but I'm using Windows and my Seeeduino is connected to 'COM6' so I changed it to 'COM6', but you will need to specify the serial port of the board you're using for programming.

I copied the Python code from the site previously linked over to IDLE and saved it, and I put the FPGA bitmap file (top_bitmap.bin) I had previously generated using iCEcube2 in the same folder as the Python file. If you don't already have Serial for Python installed then you will need to install it, which you can get from:

https://pypi.org/project/pyserial/

Click 'Download files' and click on the file under 'Built Distribution' to download it, it should be a .whl file. If using Windows, open Command Prompt, CD to the location of the downloaded file then use 'pip install' followed by the filename, e.g.:

pip install pyserial-3.5-py2.py3-none-any.whl

After a few moments it should say it successfully installed.

Then I connected up the Seeeduino Xiao to the ICE40 board in the following way (pin numbers in brackets for the ICE40):

XIAO ICE40

GND GND(2) & SS_B(10)
D7 CRESET(6)
D8/SCK SCK(9)
D10/MOSI SDI(7)

I first powered the ICE40 board (the power and two status LEDs were on and there was no response from the switches) and then I plugged the Xiao into my Surface Pro. When I ran the Python script (in IDLE Run->Run Module), two blue LEDs lit briefly on the Xiao, the TX and RX LEDs. The green Cdone LED on the ICE40 soon came on, about 4 seconds total for the whole process. Now, pressing BUT1 will light LED1 and BUT2 will turn on LED2, which is opposite of the built-in configuration when I purchased the board.

Since we only wrote directly to the FPGA, our new configuration will be lost if power is removed from the ICE40 board and it will revert to the configuration stored in the on-board flash memory. Writing directly to the FPGA is useful for testing rapid changes but once I work out how to program the flash (as the early tutorials I tried but couldn't get working showed how to) I'll be able to keep my configuration permanent.

Note that if you press the reset button (RESET1) on the ICE40 board it will become 'frozen' (it won't respond to the switches) and you will need to program it again or power cycle.

Sipeed Tang Nano Development Board

I had been looking at getting a Sipeed Tang Nano development board due to its small size and low price and seized the opportunity when I saw one on eBay for under £6 shipped (they normally sell for about £20) but although I'm pleased with my purchase, the seller had claimed it to be a Tang Nano 1K whereas it's actually the original prior model, and while similar to the 1K, the 1K has a different FPGA chip (GW1NZ-LV1QN48C6/I5), which slowed me down in getting my board fully working.

You can view a photo of the board below:

One of the attractions of the board is that it has on board a USB-C connector and the necessary circuitry to not only power the board but also provide a JTAG programming interface, although a separate programmer can be used through the provided connections, if preferred. 

The Tang Nano features a GOWIN GW1N-LV1QN48C6/I5 FPGA with the following spec.:

41 I/O
1152 LUT
864 FF
72Kb BSRAM
96Kb user flash
1 PLL

For further information please see the chip family datasheet:

https://www.mouser.co.uk/datasheet/2/1033/GW1N_series_of_FPGA_Products_Data_Sheet-1830682.pdf

Also on the Tang Nano is a 24MHz crystal oscillator, two user switches, labelled 'A' and 'B', and a user RGB LED, user RGB LCD connector, and two rows of I/O and power connections, which you can solder headers to, ideal for putting into breadboard. 

The product page can be found at:

https://tangnano.sipeed.com/en/

Note that the board is referred to as the 'Lichee Tang Nano' on the linked to site. The page includes the board pinout and links to downloads and schematic. You will also find example links on the left of the page; Lighting tutorial, Point LCD tutorial, and Use PSRAM storage, although the latter is not a clickable link.

If you click the 'GoWin official download station' link in the 'Resource download link' section you will be taken to the downloads page, which is in Chinese, but of course you can translate it but it's easier to go to:

https://www.gowinsemi.com/en/support/home/

To download the software you'll need to create a free account if you haven't already got one. Note: you will need to provide your phone number. You can then click on the Download link at the left of the page. There are a number of versions of the GOWIN FPGA Designer (the first set of download links) and programmer for Windows and Linux, as well as links to the user guides. I went with 'Gowin V1.9.9Beta-6 (Windows)' as I'm using a Surface Pro running Windows 10 - best not get the Gowin Education version, which although doesn't require a license is has limited device support, it doesn't support the original Tang Nano but does support Tang Nano 1K.

Installing the software is simple, just extract the downloaded file and run it, during the install it will also install the drivers. To use the FPGA Designer you will need a free license, which you can get from:

https://www.gowinsemi.com/en/support/license/

Annoyingly you have to put in a company name and telephone number, I made up the company name. Then you have to wait for a response (I had to wait about a day).

Once I had got the license I plugged the Tang Nano into my PC and Windows detected it and the board showed up as COM port in device manager. A red LED on the Tang Nano lit up and the RGB LED cycled through off, green, blue, and red, possibly a default configuration stored on the board (I have no idea if the previous owner had even used the board).

A couple of project examples for various Tang boards can be found at:

https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-Doc/examples.html

So I tried out the 'Blink' example, which took me to a page with 'Blink by yourself' and 'Using GitHub project' options, the former takes you through creating the project from scratch, the latter using the GitHub hosted project. I chose the latter option and ran through the instructions on the page but after selecting 'clean&Rerun  All' (right-click in the Process pane of the GOWIN FPGA Designer), in the output window it complained about 'null character in directory path', so I had to remove the space from the folder name where I stored the project. I opened up the project again, did clean&Rerun All, and this time it was successful.

A screenshot of the FPGA Designer follows, with the Blink example project opened and the schematic view displayed (Tools->Schematic Viewer->RTL Design Viewer). You can see how much complex logic is required just for a simple design.

Various html and text files are generated during the design compilation and are stored in the \impl\pnr folder, giving detailed statistics, for e.g., the file that has the extension '.rpt.html' has a Resource Usage section, revealing that the Blink example has 5% LUT utilization.

To program the FPGA, you can double-click 'Programmer' in the Process pane to launch the GOWIN Programmer software (see below), which will start with a 'Cable Setting' pop-up window (which annoyingly on my Surface it too small to read the text or select the controls without setting Windows scaling to 100%), usually all you need to do is click the 'Save' button.

Note that the version of the programmer is V1.9.9 Beta-6 Build 31030.

The 'FS File' section should have automatically been set based on your project, this file can be used either to program the FPGA's SRAM, which is ideal for rapid testing but the design will be lost when power is removed from the Tang Nano, or it can be used to program the flash memory, which takes a bit longer but isn't lost when power is removed. This is at contrast with other FPGA development boards which require a different file type for programming the non-volatile memory, and thus an extra step.

The default operation in the Programmer software is 'SRAM program'; to program the board just go to Edit->Program/Configure or use the shortcut icon, and the configuration will be downloaded to the board (which should take a couple of seconds) and run immediately.

The Blink example cycles the on-board LED red/green/blue unlike the built-in example I mentioned earlier which does the same but also switches the LED off after lighting green/blue/red, and it also cycles through the colours faster.

Back to the programmer software, to change the operation type, you can double-click on the 'Operation' section, or right-click anywhere along the row and select 'Configure Device', or go to Edit->Configure Device. In the pop-up window you can select an option from the 'Access Mode' drop-down menu, and an option from the 'Operation' drop-down list, which changes depending on the access mode. For example, to read the device ID codes, have 'Access Mode' set to 'SRAM Mode' and 'Operation' to 'Read Device Codes', then click the Save button, and then Program/Configure. You should get this report for the original Tang Nano:

Info: ID Code is: 0x0900281B
Info: User Code is: 0x0000496F
Info: Status Code is: 0x0001F020

You can find a list of ID codes on page 55 of the Gowin FPGA Products Programming and Configuration Guide:

https://cdn.gowinsemi.com.cn/UG290E.pdf

Remember originally I thought I had a Tang Nano 1K but the above information confirmed that I actually have the original model. If you get an 'Error ID code mismatch' in the Output window when trying to program then the programming file is for a different FPGA.

We can also write to the FPGAs flash memory using the programmer software, to do so change the 'Access Mode' drop-down to 'Embedded Flash Mode' and make sure 'Operation' is 'embFlash Erase,Program' (supposedly it shouldn't be set to 'embFlash Erase,Program,Verify'). Click the Save button and you will now see that 'Operation' in the main window becomes 'embFlash Erase,Program', click 'Program/Configure' to write your design to the flash memory. Except that is what is supposed to happen, but for me (and others, from what I found online) it doesn't work; after some time (about 17 seconds for me) it will report 'Program failed' in the Output window. Since the programming process erases the flash, it loses whatever was originally stored on the FPGA, so I no longer had the program that was already on it. I found I had to unplug the Tang Nano from my PC, close the programmer software, plug the board back in, launch the programmer again from the FPGA designer app, and then I could successfully program in SRAM mode again although trying flash once more failed again.

Looking online it's recommended to set the cable speed to 2.5MHz or lower, and although it was already set to 2.5MHz (Edit->Cable Setting->USB Cable Setting) I did try lower speeds, such as 0.9MHz. That apparently resulted in successful writing to the flash but the output window reported 'Finished, but wakes up failed', and unplugging and replugging the Tang Nano didn't run the supposedly flashed program.

Just in case there was a problem with the file I was trying to write, I did try a .fs file from online but got the same error. So I looked online some more and found people recommending and having success with openFPGALoader, which you can find at:

https://github.com/trabucayre/openFPGALoader

There didn't appear to be 'proper' instructions for installing openFPGALoader on Windows but I came across a guide for installing on various operating systems including Windows, which is for a different board but works also for Tang Nano:

https://fpga.mit.edu/6205/F22/documentation/openFPGA

When I got to the 'Zadig' part I had to go to 'Options->List All Devices' and selected 'Sipeed-JTAG (Interface 0)' in the drop-down and replaced the driver. I did the same for 'Sipeed-JTAG (Interface 1)'.

In MSYS2 I did the first simple test, using the 'detect' option:

openFPGALoader --detect

It reported:

idcode 0x900281b

manufacturer Gowin

family GW1N

model  GW1N-1

irlength 8

Which is the correct IDcode for Tang Nano.

Next, I tried an SRAM download:

openFPGALoader -b tangnano C:/Users/jam/led_prj.fs

Don't forget to change to your filename and path, note the program expects forward slash whereas Windows uses backslash. You can right-click in MSYS2 and select Paste rather than type out the filename and path.

To program to flash you include the '-f' parameter:

openFPGALoader -b tangnano -f C:/Users/jam/led_prj.fs

However I got multiple write errors and had to press Ctrl-C to terminate. So, as with the GOWIN Programmer, openFPGALoader was successful with an SRAM write but not flash program.

Once again back online, people were saying that a possible problem was the firmware of the board's CH55X USB chip (CH552T on the Tang Nano), that is causing the flash write issue both for the GOWIN programmer and openFPGALoader. Alternate firmware can be found at:

https://github.com/diodep/ch55x_jtag

However, I did find a solution using a different GOWIN programmer as I found a link to the download section on the Sipeed site and came across this page:

https://dl.sipeed.com/shareURL/TANG/Nano/IDE

I downloaded 'programmer2.7z', extracted, and ran 'programmer.exe' in the '\bin folder', which is 'V2.90426 Beta' and is called 'Programmer 2' in the title bar. It doesn't come up with the cable setting pop-up automatically and defaulted to 'embFlash Erase, Program'. I changed 'FS File' to the LED blink file (you can click in the box) and clicked 'Program/Configure'. Not only did it program the board quickly, it was successful, and my design ran and persisted between power cycles, further confirming the flash memory was indeed written to.

I wrote my own project from scratch based on the Blink example, which cycles through all colour combinations (without using PWM) of the Tang Nano's on board RGB LED, the zip file is downloadable from the bottom of this page, and is called 'clock_test.zip' (named such because it was a test of synchronizing events using the FPGA clock). I normally use the schematic approach to creating FPGA designs (placing individual logic blocks and linking them together) but that's not available in the GOWIN FPGA Designer and it was about time I learnt Verilog, so this project is my first time creating an FPGA design using a HDL (Hardware Description Language). It works by switching the on board red LED on and off every 4 second period, the green LED every 8 seconds, and the blue LED every 16 seconds, resulting in a cycle of many colours.

Have a look at main.v in the project, you will see that I've used three LED counters, counter_R, counter_G, counter_B, which are set to zero during reset, additionally during reset the red LED only is turned on (zero turns the LED on, one turns it off). We use the system clock pulse of 50MHz to wait for approximately two seconds using counter_R: 1/(50000000/97000000) = 1.94 seconds. The 50000000 is the 50MHz clock and the 97000000 is the 96999999 increased by one since the counter is initially zero. The three LED counters are increased by one every time counter_R reaches its maximum value (96999999).

After the approximate two seconds the red LED (led[0]) is toggled on/off, and so also is the green LED (led[1]) if counter_G is equal to one; since it's a 1-bit value it will rollover, only ever having the value zero or one. Similar, counter_B is checked to see if its value is two before toggling the blue LED (led[2]) on/off, as counter_B is a 2-bit value, it will rollover when equal to three and increased by one. The combination of the red, green, and blue LEDs turning on and off in sequence but with different timing results in a range of colours.

The Tang Nano is a neat little FPGA board which is ideal for an introduction to learning FPGAs, or for implementing custom logic or a replacement chip for an existing system, taking advantage of its small form factor. Being a fairly recent board at the time of buying the Tang Nano I thought it would be straightforward to use but as detailed, I had trouble initially programming the flash memory but I found a solution.

Waveshare Open3S500E Development Board

I paid £94.95 for the Waveshare Open3S500E package B Xilinx FPGA kit from eBay, which looks to be unused or barely used, and as far as I can tell is complete. You can view the product page at:

https://www.waveshare.com/open3s500e-package-b.htm

It has a price of $154.99 but note that the product is discontinued and appears to be from 2011 or 2012. If you click on 'PACKAGE CONTENT' you will find a listing of everything included in the package. There is no reason why you can't also use the peripheral modules with a Raspberry Pi or Arduino, for example, as long as you take into account any voltage level conversion that may be necessary. Indeed, as you will read later on, I did test a couple of the modules with an Arduino, which proved very helpful.

This is the product page for the Core3S500E Core Board:

https://www.waveshare.com/core3s500e.htm

The core board contains the Xilinx XC3S500E Spartan-3E FPGA, XCF04S flash memory for user code, 50MHz clock, power circuitry, I/O pins (which plug into the DVK600 motherboard), JTAG connector for programming/debugging, nCONFIG and reset buttons, and four red user LEDs. Because the core board can plug into an expansion board (such as the DVK600) it has a flexible approach - you could even make your own board for the core board to plug into.

For technical information about the core board as well as links to schematic, demo software, and so on please see:

https://www.waveshare.com/wiki/Core3S500E

The product page for the DVK600 'mother board' as Waveshare calls it can be found at:

https://www.waveshare.com/dvk600.htm

It has a 5V power socket (convenient to run off a USB power supply, for example), power switch, various expansion connectors for the peripheral modules or your own devices, SDRAM interface, buzzer, joystick, dedicated LCD interface and contrast adjustment pot, 1-wire interface, various jumpers, and core board connectors (for Open3S500E and others).

The board schematic can be accessed at:

https://www.waveshare.com/wiki/File:DVK600-Schematic.pdf

It seems the programmer wasn't originally included in the package so you will need to source your own if you don't already have a JTAG programmer, fortunately a programmer was included when I bought the package.

Demo software has been provided to test out the features of the FPGA and the various included modules, a direct link to the demo software can be found at:

https://www.waveshare.com/wiki/File:3S500E-Demo.7z

Once extracted, you will find the VHDL and Verilog project folders in the sub folders. These projects are the examples talked about here:

https://www.waveshare.com/wiki/Core3S500E#Example_quick_start

Note that the VHDL folder has 14 projects but the Verilog folder has 18, one more than the examples on the previously linked to page. However, the Verilog folder is missing the USB example (which is in the VHDL folder) but has 'PWM' (which is the same as the Buzzer example), and 'SDRAM' as extras.

In the main folder there is a 3S500E demo code user guide.xls, which is similar to what can be found on the previously linked to page but has some extra details and gives the correct interface name unlike the site which often specifies the wrong interface name. As I go through on this page most of the Verilog demo examples (alphabetical order based on folder name) I will mention 'site' when referring to the previously linked to 'Example quick start' site, and 'sheet' when referring to the previously mentioned xls file. Also, I should mention that a lot of the Verilog files have 'corrupted' comments, likely they were in Chinese but don't display correctly on my system (your experience may differ), some of the VHDL projects, however, have English comments in the source files.

4x4 Keypad project (key44.xise)

This is what the site says:

Connect 4x4 Keypad to 8I/Os_2 interface.
Connect 8 SEG LED Board to 16I/Os_2 interface.

Sheet:

Connect the "4x4 Keypad" to 8I/Os_1
Connect the "8 SEG LED board" to 16I/Os_2
LED turns on/off according to the pressed button

The keypad needs to be connected to 8I/Os_1 with the buttons facing up and aligned to the connector such that pins 1 (marked with the white spot on the DVK600 PCB) and 2 are skipped. Supposedly the 8 seg led board should be connected to 16I/Os_2 but it didn't do anything, the sheet  more accurately notes 'LED turns on/off according to the pressed button', as the LED board isn't used but there are files possibly related to it that begin with 'LED8' so perhaps they were included by mistake. How this example actually works: pressing a key on the 4x4 keypad causes different combination of L1 to L4 to light on the core board.

8 Push Buttons (KEY8.xise)

Site says:

Connect 8 Push Buttons to 8I/Os_2 interface.
Press the buttons on 8 Push Buttons board, and the LED status will change accordingly.

Sheet:

Connect the "8 Push Buttons" to 8I/Os_1
LED turns on/off according to the pressed button

Indeed, the 8 push buttons keypad needs to be connected to 8I/Os_1 (not 8I/Os_2 as the site indicates), pressing the buttons will change the LED status (different combinations of L1 to L4 light on the core board). Oddly, in the project, it has file joystick.v, as if it used the joystick (but doesn't), and the file is poorly formatted with no indentation, a recurring theme in the projects.

8 SEG LED Board (SEG_LED_Board_8.xise)

Neither the site nor sheet are too descriptive for this project...

Site:

Connect 8 SEG LED Board to 16I/Os_2 interface.
8 SEG LED Board shows.

Sheet:

Connect the "8 SEG LED board" to 16I/Os_2
Display something on the "8 SEG LED board"

What it actually does is count in hex on the attached LED display but with the least significant digit on the left (closest to the DVK600 board).

AT24CXX (AT24CXX.xise)

***Please completely read this section first before even attempting to try the example to avoid potentially harming the FPGA and motherboard.***

This project can be used with either an EEPROM or FRAM board, the package B examples listing online (https://www.waveshare.com/open3s500e-package-b.htm) mentions both EEPROM and FRAM examples but you only get the FRAM board, as shown in the package contents listing online.

Here is the FRAM product page:

https://www.waveshare.com/fm24cxx-fram-board.htm

The resources page (schematic, datasheet, etc.):

https://www.waveshare.com/wiki/FM24CLXX_FRAM_Board

And the product page for the EEPROM board:

https://www.waveshare.com/at24cxx-eeprom-board.htm

For resources see:

https://www.waveshare.com/wiki/AT24CXX_EEPROM_Board

They are both marked as 'AT24/FM24' and feature four jumpers for WP, and A0 to A2 (device ID), labelled on the back of the PCB. You can move a jumper to the left for logic 1 or right for logic 0.

My FRAM board has an FM24CL16B 16Kb FRAM chip and is functionally the same as the EPROM (also available from Waveshare) board but faster and with higher write endurance, but doesn't use the A0 to A2 address signals even though the schematic suggests otherwise (some FRAM chips do, however). Oddly, the schematic for the EEPROM board shows WP (Write Protect) input always connected to GND unlike the FRAM board which shows it connected to the header.

Back to the example, this is the information we get:

Site:

(I2C EEPROM)
Connect AT24CXX EEPROM Board to 8I/Os_1 interface.
Connect 8 SEG LED Board to 16I/Os_2 interface.
Two digital tubes on the 8 SEG LED Board show. One of them shows the data written to AT24CXX from pin1, pin3, pin5, pin7 of SDRAM_L header. And the other one shows the data read from AT24CXX. Please connect a jumper between pin1 and pin2 of SDRAM_R then remove it, and connect pin3 and pin4 of SDRAM_R with a jumper. Data will be written in AT24CXX, and read from it again, then shown on the 8 SEG LED Board.

Sheet:

(AT24CXX)
Connect the “AT24CXX EEPROM Board” to the 8I/Os_1 interface
Connect the “8 SEG LED Board” to the 16I/Os_2 interface 
Use the "8 SEG LED board" to display the data sent from H1 pins 1, 3, 5, 7 to "AT24CXX", and the data "AT24CXX" received, using one 8-segment digit for each data.
Short the H2 pin 1 and pin 2, then open them again, lastly short the H2 pin 3 and pin 4,data will be written into AT24CXX and then read from it to display on the "8 SEG LED board".

Remark 3:
In the demo code, initially the H1 3, 5, 7, is set as pull-up input high-level, the H1 2, 4, 6, 8 is set as output low-level. It is possible to config the written data by shorting the pins 1-2, 3-4, 5-6, 7-8 respectively using jumper caps.

To connect the AT24/FM24 board to the DVK600's 8I/Os_1 interface line up VCC on the AT24/FM24 board to pin 1 (white dot) on the DVK600, and the 8 SEG LED Board to the 16I/Os_2 connector. After downloading to the FPGA you will see '0' and 'F' alternate between two of the 7-segment digits. But the instructions on the site are wrong:

'Please connect a jumper between pin1 and pin2 of SDRAM_R then remove it, and connect pin3 and pin4 of SDRAM_R with a jumper. Data will be written in AT24CXX, and read from it again, then shown on the 8 SEG LED Board.' On the sheet it refers to 'H2'.

Placing a shunt on pin 1 and 2 of the SDRAM_R connector shorts the 3.3V supply to GND. It seems they are using the pin numbering on the DVK600 which has the power supply connections at a different end.

If we look at the constraints file (AT24CXX.ucf) we can see 'wr_input' (153) and 'rd_input' (151). I/O 153 is pin 3 on SDRAM_R connector (P2 on core board schematic) and 151 is pin 5 on SDRAM_R. I tried connecting pin 3 to pin 2 (GND) and then pin 5 to pin 2 and the display changed to alternating 'F' between the two digits. One digit of the display is supposed to show the data written and the other shows the data read, so originally there must have been a 'zero', then 'F' was written, and now both digits show 'F' since that was written. However, I pressed reset on the core board and it still showed alternating '0' and 'F'.

Look again what it says on the sheet it refers to remark 3 for this project, which says:

'In the demo code, initially the H1 3, 5, 7, is set as pull-up input high-level, the H1 2, 4, 6, 8 is set as output low-level. It is possible to config the written data by shorting the pins 1-2, 3-4, 5-6, 7-8 respectively using jumper caps.'

Again, looking at the constraints file, data_in[0], data_in[1], data_in[2], data_in[3] are pullups and are assigned to I/O P9, P12, P16, P19 respectively, are are pins 4, 6, 8, and 10 on SDRAM_L (P1) on schematic. data_in[] is defined as input in i2c.v. In AT24CXX.ucf dgnd[0], dgnd[1], dgnd[2], dgnd[3], dgnd[4], dgnd[5] are assigned to I/O P8, P11, P15, P18, P160, and P152 respectively. In i2c.v dgnd[] is set as output and to all bits zero.

So the correct instruction is to short pins 3 and 4 and then 5 and 6 of SDRAM_R, which does a write then a read. Then it changes to alternating 'F' on both digits. For setting the data to be written,  you need to short on SDRAM_L pins 3 & 4, 5 & 6, 7 & 8, and 9 & 10, for bits 0 to 3. With no shunts, 'F' written, the input pins float high, so if, for example, we place a shunt on 3 and 4 of SDRAM_L and then trigger the write, you'll see 'E' alternate on the display (that is, 'E' is written). If we put a shunt on all input pins, zero will be written and displayed.

So the first digit of the display (closest to DVK600) shows the value read from the AT24/FM24 board, the second digit is the data to be written, set by the input pins; removing/adding shunts on SDRAM_L will update the display second digit immediately. It turns out the first digital of the display defaults to zero, so it may appear that the memory isn't being written to. To confirm that it is, write a value, then press reset on the core board or power cycle and download the program again. A '0' will appear on the first digit, place a shunt on 5 and 6 on SDRAM_R, which will do a read, the first digit should show the value that was previously written.

If you move the WP shunt to the '1' position and do a write and then a read you should see that indeed the value wasn't written successfully and thus the write protect is working.

Looking some more in i2c.v it says:

'if PIN_45 have been putdown ,then the seg will display  0f 0d 0b 07' but I/O 45 isn't used - it's possible the code was also for another board.

AT45DBXX (AT45DBXX_SPI.xise)

The AT45DBXX flash board product page can be found at:

https://www.waveshare.com/at45dbxx-dataflash-board.htm

Along with resources:

https://www.waveshare.com/wiki/AT45DBXX_DataFlash_Board

My particular board has an AT45DB041E 4Mb SPI flash chip.

Site says:

Connect AT45DBXX DataFlash Board to 8I/Os_2 interface.

LEDs will show the data written to AT45DBXX DataFlash Board as binary, and then show the data read from the board as binary.

Sheet:

Connect the "AT45DBXX DataFlash Board"to the 8I/Os_1 interface

The data written to AT45DBXX DataFlash Board will be showed by LEDs,then The data read from AT45DBXX DataFlash Board will be showed by LEDs

The sheet says to connect dataflash board to 8I/Os_1 and indeed the flash board should be connected to 8I/Os_1, make sure VCC of the flash board lines up with pin 1 of the DVK600. After downloading the program it will show values in binary at high speed being written to flash on L1 to L4 of the core board and then show on the same LEDs at a slower rate the data read back (which should be the same pattern) and then turn all the LEDs off. You can press the reset button on the core board and it'll repeat the operation.

Buzzer (Buzzer.xise)

The site says:

Plug in the jumper on Buzzer JMP.

Buzzer will buzz.

Sheet:

Short the Buzzer jumpers

The buzzer starts to make a sound

This is a very simple example, it sounds the buzzer on the DVK600 - as instructed, make sure the buzzer shunt is in place.

DS18B20 (DS18B20.xise)

The site says:

Connect DS18B20 to 1-WIRE port.

Connect 8 SEG LED Board to 16I/Os_1 interface

8 SEG LED Board will show the temperature accordingly.

Sheet:

Connect the DS18B20 to the ONE-WIRE socket

Connect the “8 SEG LED Board” to the 16I/Os_2 interface  (Verilog demo)

"8 SEG LED board" displays temperature

The sheet says to connect 8 SEG LED Board to 16I/Os_2, which is actually what you should do. Make sure you plug in the DS18B20 matching the body outline shown on the motherboard.

After downloading the design, you'll see the current temp shown on the 7 segment display - appears to be in deg. C. You can easily test the example is indeed working by pressing the temperature sensor between your fingers, which should cause the reading to increase and then drop slowly when you release. Note that if don't have the sensor connected when power on and transfer the program, '20.90' is displayed. 

JOYSTICK (JOYSTICK.xise)

Site says:

Plug in the jumper on JOYSTICK JMP.

Control the joystick, and the LED status will change accordingly.

Sheet:

LED status keeps changing according to the joystick pressed

The jumpers referred to are labelled A to E above the joystick on the DVK600. Pressing one of the four directions or the centre button (referred to as 'key_z' in joystick.v) causes different combinations of LD1 to LD4 to light on the core board.

LCD1602 (LCD1602.xise)

Site says:

Connect LCD1602 to LCD1602 interface. Please note that the No. 1 pin of LCD should be plugged in the hole marked with "1". LCD1602 will show.

Sheet:

Connect the LCD1602 to the LCD1602 interface, The LCD1602 pin 1 should correspond to the PCB printed mark "1" beside the onboard LCD connector

Display something on the "LCD1602"

The LCD is connected to the 20x2 connector next to the LCD contrast trimmer (LCD_VO), line up pin 1 of the LCD with the pin marked 'GND', the pinout of the LCD is also given on the PCB's underside. You can plug into either of the rows. Be very careful not to misalign the pins as the LCD could be damaged. Unfortunately, I accidentally missed the LCD pins by 1 when I put the LCD into the connector and didn't realise until after I powered on, since nothing was displayed. After powering off and connecting the LCD correctly, 'Waveshar' only was displayed. I tested the LCD with an Arduino and it worked fine, displaying text on both lines, however, the backlight behaved oddly, which I also noticed when I put the LCD back into the FPGA board. The backlight would only adjust slightly but if I turned it up all the way and powered on the contrast would be really high and then I could turn it down. Possibly I damaged something on the LCD, however, the LCD was working with the Arduino but I have been unable to get it working again with the FPGA board. I tried a second LCD module in the FPGA board and it didn't even work, but a third and fourth one did every time. It's possible that due to the way the FPGA initialises the LCD it sometimes doesn't work, additionally, 3.3V is used to power the board and 3.3V signals to interface with the LCD, which may be borderline for some LCDs to be interpreted as logic 1.

In LCD1602.v we can see a reference to 'www.21eda.com', if we Google the URL we get an indication of possibly a website that sold the kit. LCD_N and LCD_P are likely for LCD backlight. Looks like in the Verilog file (LCD1602.v) they use a case like a loop to initialise the LCD and then display 'Waveshare', which is what the example is supposed to do.

LCD12864 (LCD12864.xise)

The site says:

Connect LCD12864 to LCD interface.

LCD12864 will show.

Sheet:

Connect the LCD12864 to the LCD12864 interface

Display something on the "LCD12864"

The display is 128 x 64 dots with an LED backlight, and has a similar interface to an HD44780 LCD but with additional pins PSB (Serial/Parallel Selection), RST (Reset), Vout (LCD Voltage Doubler Output - not used in the example) as extra pins. The interface commands are similar too but there are additional ones as well.

The LCD packaging reads:

SKU: 4661

LCD12864-ST (3.3V)

The LCD has a Waveshare sticker on back of module as well as '12864ZW' on another sticker. This is the product page:

https://www.waveshare.com/lcd12864-st-3.3v-blue.htm

A link to the datasheets for the controller ICs can be found at the bottom of the page.

Make sure to insert the display the correct way into the DVK600 and not misalign the pins; you can plug the LCD into either row on the connector. After downloadint the program to the FPGA, 'Waveshare' should appear - it's a shame the example doesn't display any graphics as such

(the display has built in support for text) but that would have complicated the example. More of a concern is that I noticed flickering when viewing the display even head on but especially at an extreme angle. In the Verilog code they are continually looping but when I disabled that and redownloaded there was still flickering.

To investigate the flickering further I tested the display with an Arduino using this tutorial:

https://www.electronicshub.org/interfacing-128x64-graphical-lcd-with-arduino/

I powered the display off 3.3V and connected the backlight straight to 3.3V and GND. I found that if I used a limiting resistor for the backlight I would get regular flicker so perhaps the fault with the FPGA board is powering the backlight off I/O pins. Oddly, the contrast pot I had wired up when using the display with the Arduino appeared to have no effect.

LED (LED.xise)

I did not try this one out as looking at the code it appears to be the one that was already programmed into the board, in which all LEDs turn on and then each one turns off in sequence.

PCF8563 (PCF8563.xise)

The product page for the PCF8563 RTC (Real-Time Clock) board can be found at:

https://www.waveshare.com/wiki/PCF8563_RTC_Board

Has a header with shunt so can power the PCF8563 either off the VCC header pin or the on board battery, and there's also a header for 'INT' (interrupt - explained on linked site in FAQ section), and 'CLK OUT'. An additional I2C board can be plugged in.

The site says:

Connect PCF8563 RTC Board to 8I/Os_2 interface.

Connect 8 SEG LED Board to 16I/Os_2 interface.

8 SEG LED board will show the time information

Sheet:

Connect the "PCF8563 RTC Board" to 8I/Os_1

Connect the “8 SEG LED Board” to the 16I/Os_2 interface

The RTC board should indeed be connected to 8I/Os_1, be sure to align VCC of the RTC board with pin 1 (white dot) of the DVK600. After downloading to the FPGA the display will show time counting up in seconds and minutes from 0. If we move the shunt from 'VCC'  to 'BAT', power on the board and redownload the program, and repeat, it will continue from the current minute, but strangely seconds will always start at 0. 

It looks like pcf8563.v handles communication with the RTC module, pcf8563_seg7.v is the top module (which oddly is named ds18b20_seg7), and seg_dynamic_drive.v handles the display. Q_KEY (which is a reset signal) is referenced in pcf8563.ucf but never used. In pcf8563.v it looks like they just read the minutes and seconds, there is no writing to the RTC module.

If power off and move the shunt back to 'VCC', power on and program again, it will start on 0. If don't have the RTC board plugged in the display will always show 'FFFF' (which it will initially show even if have the RTC board plugged in).

To further test the module, I tried it with an Arduino Uno, using the PCF8563-Arduino-Library:

https://github.com/Bill2462/PCF8563-Arduino-Library

I used the 'simple' example but commented out the code in the setup() to prevent changing the date and time. With the RTC board shunt on VCC, when plug in and enter the Arduino serial monitor the date and time starts at a random value but the time increases as expected. If then powered off, moved the RTC shunt to BAT and powered on again, the time resumed, powered off and on again and the seconds were correct. Thus the FPGA code must have been doing something funky to cause the seconds to reset each time. 

Note that it's a good idea to put the RTC shunt back on VCC when not in use to save battery life.

PCF8591 (PCF8591.xise)

The product page for the PCF8591 'AD DA' (A/D Converter and D/A Converter) board can be found at:

https://www.waveshare.com/wiki/PCF8591_AD_DA_Board

The site says:

Connect PCF8591 AD DA Board to 8I/Os_2 interface.

Connect 8 SEG LED Board to 16I/Os_2 interface.

The two digital tubes on the right show AOUT pin voltage from PCF8591. If any voltage is detected from AIN0, the two digital tubes on the left show a hex number according to the voltage AIN0 is supplied with. If no voltage is detected from AIN0, the two digital tubes on the left show a hex number according to the voltage from AOUT.

Sheet:

Connect the "PCF8591 AD DA Board" to 8I/Os_1, and connect a keyboard

Connect the "8 SEG LED board" to 16I/Os_2, and connect a keyboard

Very odd why it says to connect a keyboard since it's not needed. However, the sheet is right in that the PCF8591 module needs to be connected to 8I/Os_1.

I connected a potentiometer centre connection to AIN0, and its other two connections to VCC and GND of the PCF8591 board, and a voltmeter between AOUT and GND. After powering on the FPGA board and downloading the program, I found that adjusting the pot resulted in the display left two digits showing the AIN0 ADC value in hex, from 00 to FF hex depending on the wiper position. I did notice some ghosting on the display but wasn't sure if that was normal for the way the display is being updated. Note that the value isn't the analog voltage as suggested by Waveshare but the 'raw' value. It's not explained by Waveshare but the AOUT voltage is constantly increased by the FPGA design, starting on hex 7F (about 1.6V), increasing to FF (about 3.2V), and then counts again from 0 (0V). The AOUT value is shown on the right two display digits but again, the value isn't the voltage.

As can be found in the PCF8591 datasheet, the IC's I2C 7-bit base address has the upper 4 bits set to 1001 but the A0 to A2 headers on the PCF8591 can be used to set the lower 3 bits of the address using shunts. For example, if the A0 shunt is placed in the '+' position, the I2C address becomes hex 49. You can see this yourself by, for example, using an Arduino acting as an I2C bus scanner:

https://learn.adafruit.com/scanning-i2c-addresses/arduino

In the FPGA verilog code, file pcf8591.v, you will find the I2C address referenced as hex 90 rather than 48 since an 8-bit value's expected. 

Write address:

slave_address1=8'b10010000

The read address is one more than the read address:

slave_address2=8'b10010001

Strangely, some parts of pcf8591.v have been commented out but possibly leftover code from another project using similar 'mechanisms'.

The PCF8591 board has a header and shunt for selecting VREF between the on-board pot (AD0) and VCC, annoyingly the plastic part of the pot broke off, but still operational, so be careful.

The FPGA example only shows a little of what the pcf8591 board can do, it would be a good idea to adapt perhaps to show all four analog inputs on an LCD. However, if you want to quickly test your module is working you could use an Arduino and sketch:

https://www.instructables.com/Arduino-and-PCF8591-ADC-DAC-IC/

PS2 (PS2.xise)

The product page for the 'VGA PS2' board is at:

https://www.waveshare.com/vga-ps2-board.htm

The site says:

Connect VGA PS2 Board to 16I/Os_2, then connect a PS/2 keyboard to the PS/2 port of the module board.

Connect LCD1602 to LCD1602 interface. Please note that the No. 1 pin of LCD should be plugged in the hole marked with "1".

LCD1602 will show the input by PS/2 keyboard.

Sheet:

Connect the "VGA PS2 Board" to 16I/Os_2, and connect a keyboard

Connect the LCD1602 to the LCD1602 interface, The LCD1602 pin 1 should correspond to the PCB printed mark "1" beside the onboard LCD connector

Characters inputted from keyboard are displayed on LCD1602

The 'VGA PS2' Board supplies 3.3V to the keyboard so possibly some keyboards may not work, fortunately, I was able to use my Sega Pico keyboard, which I knew works on 3.3V but being a Japanese keyboard it makes testing a bit more difficult. Pressing a key on the keyboard causes the key to appear on the LCD (the first character didn't appear until after a few presses), shifting along one character at a time and moving on to the next line automatically but oddly after the 13th character, so only 26 characters can be displayed. Strangely, a few of the LEDs on the core board turned on/off when pressing certain keys on the keyboard and sometimes, when powering on the FPGA board before even programming it, characters appeared on the LCD.

I tried with a Raspberry Pi keyboard and USB to PS/2 converter but that didn't work, possibly either the converter won't work at 3.3V or the keyboard doesn't support PS/2 mode. In the end I used a Compaq PS/2 keyboard but even with that keyboard, I had to press a key twice before the first character apears. Caps lock is supported, although the keyboard's caps lock light isn't used and you have to press it twice to turn caps lock on. The core board L2 will light when caps lock is pressed but will go out if a character key is pressed but pressing the caps lock multiple times, while maintaining caps lock status, L2 will remain on. In fact, it seems L2 lights whenever 'special' keys are pressed, such as scroll lock, insert, enter, shift, space, etc. Note: space doesn't insert a space.

Certain keys cause L3 to light when held down; Windows, ctrl, whereas others latch the LED until shift is pressed (function keys, for example). You can hold a key and the character will be entered at high speed. Backspace deletes previous characters. Pressing either shift key and then a number key (no need to hold down shift) will generate the shifted version of the key, however, I couldn't find how to turn that off.

ps2.v appears to handle the PS/2 interface and lcd.v handles updating the LCD based on the keys pressed. Oddly, the core user LEDs aren't in the constraints file (PS2.ucf) although there is reference to vled in ps2_top.v but is only assigned all 1s, and can be seen if open open PlanAhead, but no FPGA pins are assigned. Generating the programming file and using that produces the same results.

Looking at lcd.v we can see that keynum keeps track of where the next char is displayed and is indeed limited to 26 positions, it's strange why they didn't use the full 32 characters.

In the VHDL version the core board LEDs remain on but it doesn't respond to backspace, caps or shift, and there is no auto repeat, but does use all 32 chars. In the project: ps2.vhd the comments tell us that it was originally written for the FPGA-evb-S2 Xilinx Spartan-II evaluation board, and that 'This example reads scan codes from a PS/2 keyboard and displays them on LEDs', rather than the LCD but they probably didn't bother to update the comment. Indeed the keyboard handling code in ps2.vhd is a lot simpler than the Verilog version.

PWM (Buzzer.xise)

The site says:

Plug in the jumper on Buzzer JMP.

Buzzer will buzz.

Sheet:

Short the Buzzer jumpers

The buzzer starts to make a sound

That's exactly what it does, however, it's not using PWM in the way you would expect. The design simply toggles the buzzer on/off when a fixed count value is reached. It's very similar if not the same as the 'Buzzer' example ('Buzzer Test' on the site); the sheet groups both 'Buzzer' and 'PWM' as the same.

sdram (testsdram.xise)

This example isn't  mentioned on the site or sheet, and package B doesn't come with a suitable SDRAM board. Interestingly, the package B I bought second hand came with a DRAM board but with a PMOD connector, so not directly compatible with the DVK600 (perhaps it was bought in error). This looks to be the required board:

https://www.waveshare.com/SDRAM-Board-B.htm

Since I didn't have the required board I didn't get to try this example.

UART (UART.xise)

The product page for the UART board:

https://www.waveshare.com/pl2303-usb-uart-board-mini.htm

The board is labelled as 'PL2303' (which is the IC part number). 

The site says:

Connect the pin side of RS232 Board to 8I/Os_1, and the other side to PC's serial port.

Connect 8 SEG LED Board to 16I/Os_2 (Only connect in VHDL Test).

Run PuTTY to communicate with serial(Baud rate:9600bps). Sending any strings will cause same strings receiving from PuTTY.

Sheet:

Connect the "RS232 Board" to 8I/Os_1, then connect it to PC

Connect the "8 SEG LED Board" to 16I/Os_2

In the Verilog file can be found:

Send any character/number via "Serial Port Monitor", and it should be sent back and displayed on "Serial Port Monitor" again.

Also:

Launch the "DVD_XILINX_EN\data\Software\sscom32\Serial Port Monitor.exe", select a proper COM port, config the speed as 9600

Perhaps the 'Serial Port Monitor' is to be used instead of PuTTY but I don't have the program.

I first tested the module on its own by connecting it to my PC via USB and with a shunt on TXD and RXD. The PWR LED lit and the device appeared in the device manager as a COM port, the drivers were installed automatically. If you need the driver it can be found at:

https://www.waveshare.com/wiki/PL2303-USB-UART-Board_Software

To test, open PuTTY and open a serial connection at 9600 speed with the COM port of the device. Whatever you type should appear immediately and the RXD and TXD LEDs should blink.

Going back to the FPGA board since I was trying out the Verilog example I only connected the UART Board to the DVK600 but I made sure that the VCCIO shunt was removed from the UART board, which ensures the DVK600's VCC wasn't connected to the 3.3V generated by the PL2303, which is powered by the USB mini connector. After downloading the example program to the FPGA, connect the UART board's USB mini to the PC and open PuTTY in the same way as before. Again, you should see the characters you type in the PuTTY window along with the RXD and TXD LEDs flashing on the board.

VGA (VGA.xise)

The product page for the 'VGA PS2' board:

https://www.waveshare.com/vga-ps2-board.htm

Note that there are on board resistors that form a simple DAC.

The site says:

Connect VGA PS2 Board to 16I/Os_2 interface, then connect a VGA disply to the VGA port of the module board.

VGA display will show.

Sheet:

Connect the "VGA PS2 Board" to 16I/Os_2, and connect a VGA monitor.

Display something on the VGA monitor

The example displays light yellow, darker yellow, dark green vertical bars, then the rest of the screen is light green (over 50%). Looking at VGA.v you can see that 3 bits are used for red and green, but only 2 bits for blue, possibly so the whole colour value fits in 8 bits:

assign {red0,red1,red2,green0,green1,green2,blue0,blue1} = (dat_act) ?  data : 3'h00;

We can see the colours being assigned depending on the horizontal position:

always @(posedge vga_clk) 

begin

 if(hcount < 223)

  data  <= 8'b11111111;       

 else if(hcount < 303)

  data  <= 8'b11111100;   

 else if(hcount < 403)

  data  <= 8'b00011100;   

 else if(hcount < 783)

 data  <= 8'b01111100; 

 else 

  data  <= 8'b00000000;   

end

USB (USB.xise)

This example only has a VHDL version so I will discuss it here.

Product page:

https://www.waveshare.com/cy7c68013a-usb-board-mini.htm

You can find links for the schematic, software, etc. on the page.

Wiki:

https://www.waveshare.com/wiki/CY7C68013A_USB_Board_(mini)

Of particular interest is the 'Design Resources' link which takes you to 'How to reprogram the serial EEPROMs on the CY7C680A board' application note, and 'Demo Firmware' which is what is used in the USB FPGA example.

The CY7C68013A USB Board has its own 3.3V voltage regulator, likely to put less strain on the FPGA board. There is an EEPROM chip which the CY7C68013A loads its firmware from, power LED, two user LEDs, reset switch, 2x2 header for 3.3V and GND, and header with shunt to disconnect the on board EEPROM.

The site says:

Connect the pin side of CY7C68013A USB Board to 32I/Os_1 interface, and connect the USB side to PC's USB port.

Run USB_LED.exe on the PC to control onboard LED.

Sheet:

Connect the "CY7C68013A USB Board" to 32I/Os_1, then connect it to PC

Control the onboard LED via USB_LED.exe

Remark 2:

1. Install driver "data\Software\USB Driver\EZ-USB.exe"

2. Open the project "data\program\3S500E\VHDL\USB\USB.xise"

3. Download the firmware "usb_led.bit" to the development board

4. Launch "data\software\USB VC\Release\USB_LED.exe"

Unfortunately, the USB_LED.exe file isn't included with the demo software. However I found it here:

https://www.waveshare.com/wiki/XILINX_Software

Download USB-VC.7z, extract it and in the 'USB VC' folder you will find what looks to be source code, and in the Release subfolder you will find the USB_LED.exe file.

After downloading the example program to the FPGA and plugging the mini USB from the CY7C68013A USB Board into my PC, Windows detected it as 'EZ-USB FX2' but did not install the drivers. The driver can be found at:

https://www.waveshare.com/wiki/CY7C68013A-USB-Board_Software

The file is 'CySuiteUSB_3_4_7_B204.7z', you need to follow the instructions in 'CY7C68013A_USB_Board_Driver_Install.pdf'. Unfortunately the screenshots in the PDF feature Chinese text so I will run through what I did. This involves running CySuiteUSB_3_4_7_B204.exe and through the installation, annoyingly you have to enter a user name and company name. Then you have to open go to Device manager, right-click 'EZ-USB FX2', select properties. Click 'Details' tab, and on the 'Property' drop-down choose 'Hardware IDs', make a note of the VID and PID numbers (see the screenshot in the PDF), for me they are 0547 amd 1002 respectively. Next, navigate to the driver directory folders where the Cypress suite was installed (see screenshot in PDF). Look for the subfolder for your opearting system, although I'm using Windows 10 64-bit, I opened the 'wlh' sub folder, and then 'x64' folder. Then have to open 'cyusb.inf' in notepad, in section 'for x64 platforms', under '[Device]' remove the semicolon from the start of the next line and then change the two occurrences on that line from 'VID_XXXX&PID_XXXX' so that the first 'XXXX' is replaced with the VID & PID values you found in the device manager. Mine looks like this:

%VID_0547&PID_1002.DeviceDesc%=CyUsb, USB\VID_0547&PID_1002

Then save the file.

Next, back in Device manager, reload the driver by right-clicking on 'EZ-USB FX2' and selecting 'Update driver', click 'Browser my computer for drivers', click 'Let me pick from a list of available drivers on my computer'. Click 'Next', click the 'Have Disk...' button, click the 'Browse...' button and navigate to and select the 'cyusb.inf' file that you previously modified, click 'OK' button. Then click 'Next' button, you may get this error message: 'The Third-party INF doesn’t contain Digital Signature Information'. The fix can be found on this site:

https://appuals.com/how-to-fix-the-third-party-inf-doesnt-contain-digital-signature-information/

I followed the instructions in section 'Solution 2: Disabling Driver Enforcement through Command Prompt'. However I got this error: 'The value is protected by Secure Boot policy and cannot be modified or deleted.' While I could have tried to sort that I looked online to see if that was a more recent version of the suite. However I came across this site which has drivers up to Windows 10:

https://community.infineon.com/t5/Knowledge-Base-Articles/Drivers-for-EZ-USB-FX1-FX2LP-and-FX3-KBA94413/ta-p/248634

Click on 'Drivers.zip' - need to be an Infineon member but is free to sign up.

Extract the downloaded file and then go through the process of manually selecting the driver but when you click on the 'Have Disk...' button, navigate to the cyusb3.inf file in the appropriate folder for your operating system from the file you just extracted, example, Win10\x64. Select 'Cypress EZ-USB NX2LP-Flex BootLoader Device' (not sure if that's the correct option) then click the 'Next' button, Windows may warn that installing the driver is not recommended but click 'Yes' anyway.

Next I unplugged the USB board from my PC and plugged it back into the FPGA board, downloaded the program to the FPGA, and plugged the USB board back into my PC. Then I ran USB_LED.exe, Windows popped up with a message which is garbled (likely saying it can't find the USB board), clicked 'OK' and was taken to main window with buttons for operating the LEDs, none of which did anything except causes a '??' message, which shuts down the program. I tried installing other device drivers from the list but no joy and in the instructions they show a generic driver.

Looking at USB_LEDDlg.cpp in the 'USB VC' folder we can see that an attempt is made to open a device called 'EZUSB-0' using the Windows CreateFile() function even though the device I'm using shows up in CyConsole. This makes me wonder if USB_LED.exe was designed for an old USB board?

I did also follow the instructions to reprogram the firmware:

https://www.waveshare.com/wiki/Using_CySuiteUSB_3_4_7_B204_reprogram_the_firmware_manual

But it made no difference.

I eventually came across:

https://www.catalog.update.microsoft.com/Search.aspx?q=Cypress+Generic+USB+Driver

I downloaded 'Cypress - Other hardware - Cypress USB Generic Driver (3.4.7.000)' (the 118KB version, the 45KB version didn't work); click the Download button and then click on the .cab file. After downloading use a program such as 7-Zip to extract, then manually add it as the USB Board's driver (Have disk...), for the Model select 'Cypress USB Generic Driver (3.4.7.000)' and click Next. Windows will warn that you need to restart your computer for the hardware to work, but not needed, click 'No' when prompted. You should see in the Device manager the USB board now shows up as 'Cypress USB Generic Driver (3.4.7.000)'. You will need to uplug and replug the USB board to avoid restarting the computer. However, it still didn't work so I'll have to try something else some other time, perhaps on another computer to see if that makes a difference, but either way the USB board is useful even as a standalone board with custom firmware.

FPGA Tips and Solutions

Please note that certain issues and the solutions/workarounds may only be applicable to certain versions of the software.

Nios II Eclipse Error: cannot step through your code in debug mode

Solution: open Debug window Window->Show view->Other... Select 'Debug' from the 'Debug' folder and click 'OK'.

Nios II Eclipse Error 'No Nios II target connection paths were located'

Solution: close Eclipse and open again, then try Run as again.

Quartus Error (12006): Node instance...

I had created an SDRAM controller using Qsys and after generating it and adding it to my design when I tried to run Analysis & Synthesis I got this error:

Error (12006): Node instance "inst90" instantiates undefined entity "sdram_controller". Make sure that the required user library paths are specified correctly. If the project contains EDIF Input Files (.edf), make sure that you specified the EDA synthesis tool settings correctly. Otherwise, define the specified entity or change the calling entity. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

The solution:

Assignments->Settings... Category: Files. To the right of the File name: box click the '...' button and select the files that make up the component, which for me was sdram_controller.cmp and sdram_controller.qip. After clicking the open button you are returned to Settings and then it's a matter of clicking the Apply and OK buttons. You will see the files you selected added to the Files view of the Project Navigator area and running Analysis & Synthesis again shouldn't see the error return.

Quartus MegaWizard PLL cannot remove reset input

If you create a PLL using the IP Catalog provided by newer versions of Quartus you will find that the PLL must have a reset input even though in older versions of Quartus that was not the case. You can either leave the reset input unconnected (Quartus will warn that it's not connected) and set the PLL to auto reset (MegaWizard Settings tab: PLL Auto Reset On) or drive the reset input using appropriate logic.

Quartus MegaWizard plug-In not available

As of Quartus V14.1, the MegaWizard (Megafunction wizard) was removed and has been replaced with the IP Catalog. If the IP Catalog is not already visible then select View->Utility Windows->IP Catalog. To add a component to your block diagram/schematic select it from the IP Catalog and either double-click or click the Add... button which will cause the Save IP Variation pop-up to appear. Select the type of file you want (VHDL/Verilog) and give the component variant a name (cannot be the same as the component) in the IP variation file name box, after the specified path. Then the familiar looking MegaWizard will launch where you can customise the settings of the component variant and click the Finish button when done. To add the component variant to your design select to insert a symbol (right-click, Insert->Symbol...), expand Project under Libraries, choose your design and then click the OK button.

Don't forget that if you need to make changes to your component variant you can double-click it once added to your design to launch the MegaWizard again.

Quartus Warning 'Output pins are stuck at VCC or GND'

While there are many issues that can cause the above warning after either running Analysis & Synthesis or starting compilation, the particular issue I was having was that no matter what I did to my design Quartus would always see outputs as stuck to GND (you have to expand the warning to see if the individual I/O is stuck at VCC or GND). Eventually I realised the issue which was very subtle but is a reminder of often a simple mistake leading to many problems. The reason for the supposed stuck pins was due to naming the schematic file differently to the project level name (or top-level design entity name if different from the project name). So effectively Quartus wasn't seeing my design and thus the I/O was defaulting to a stuck state since they weren't connected to anything. If you ever do this yourself, although you cannot rename the file in the Project navigator area you can copy your design to a new file, save it with the correct filename and then remove the incorrectly name file by right-clicking it and selecting Remove File from Project.

Quartus Warning 'Timing requirements not met'

One reason for the above warning is that a default TimeQuest file has not been created and without such a  constraints file, Quartus assumes all clocks in the design run at 1GHz, most likely causing the previously mentioned warning. To add the required file:

Tools->TimeQuest Timing Analyzer

File->New SDC file which opens Text Editor. Add the required code. For e.g.:

create_clock -period 20.000 -name osc_clk osc_clk

derive_pll_clocks

derive_clock_uncertainty

Save the file with the top-level name of your project (so it becomes the default TimeQuest file) using File->Save.

For more information about a few of the important commands:

derive_pll_clocks

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/tafs/tafs/tcl_pkg_sdc_ext_ver_1.0_cmd_derive_pll_clocks.htm

derive_clock_uncertainty

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/analyze/sta/sta_db_derive_clock_uncertainty.htm

create_clock

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_create_clock.htm

Send/attach to a site a Quartus project

If you want to email someone or attach to a site a Quartus project with only the necessary files then you can do the following:

Open the project in Quartus. Then select Project->Copy project... Choose a destination directory and enter a new project name, then click OK. Go to the project folder in Windows explorer and select all of the files and folders except 'incremental_dub' and 'output_files' and send the files to a zip file (Right-click->Send to->Compressed (zipped) folder).

Alternatively, you can:

Open the project in Quartus and click Project->Archive project... Enter the file name to use as the archive file name and click Archive. If you want to open the archived file go to Project->Restore Archived Project...

Nios Soft Core Processor

For a project I was looking at creating a complete computer-like system (CPU, GPU, RAM, etc.) at a small size and using an FPGA seemed like the best way to go. I had considered using a Raspberry Pi Zero but it was off putting because of the slow boot time and I really wanted to design my own system. As I owned a Cyclone II development board I looked at whether there was a soft core processor (a CPU realised in an FPGA) available for the FPGA. I eventually came across the Nios II processor, a 32-bit RISC CPU, the successor to the 16-bit Nios processor. These Nios processors are a form of System On Programmable Chip (SOPC) because the CPU is implemented in FPGA logic elements and can co-exist with any other system building blocks created on the FPGA.

While it proved to be very difficult to actually implement a Nios processor on an FPGA I kept at it and eventually got the processor to blink an LED, a simplified 'Hello World' if you will. One of the tutorials that I followed you can find at:

There are two main steps in getting the Nios onto an FPGA:

1. Create the design: putting together the logic blocks that make up the Nios CPU and other system blocks. This is done using Quartus II. The design is then downloaded to the FPGA.

2. Write code (C/C++) for the Nios CPU to run. Nios II software build tools for Eclipse can be used for this. If the design from step 1 was downloaded to the FPGA and is running then the Nios code can be downloaded to the soft core. After a few moments the Nios processor will then run the downloaded code.

Having a processor run on an FPGA is one thing but we need to get it to do something useful that we can see. During step 1 we can add a Parallel Input/Output block and connect an LED to it which the processor can then turn on/off.

To create the Nios system in Quartus we use Qsys (Tools menu), which is a software tool that helps with the connecting of different sub systems. In the tutorial I followed, the following elements were used: clock, PLL, Nios CPU, RAM, JTAG, system ID and PIO. Note that JTAG is needed for downloading the processor software to Nios on the FPGA and the system ID ensures that you can only download software to the Nios design it was intended for.

Because the Nios CPU uses some of the FPGA's logic blocks we have to be careful that we don't use up all of the FPGA's resources, especially if you want to add other system blocks to the FPGA (GPU, for e.g.). I found that my C test program which simply turned an LED on/off took up 6K of RAM (remember, that's RAM emulated in the FPGA), which was almost all of the RAM I had created. Of course, there are ways to cut down on the amount of RAM used and certainly writing the code in assembly language is one option. You can also add additional RAM outside the FPGA and interface to that memory using the FPGA's I/O.

Just as you can write your design permanently to the flash memory used by an FPGA you can also write the Nios software to non-volatile memory and have the Nios boot from that memory.

PLL Introduction

FPGAs are clock driven devices and because of that simple fact you may have come across the PLL (Phase-Locked Loop) but perhaps not quite grasped what its purpose is. In simple terms, a PLL is used to generate clocks of a specific frequency that would otherwise be difficult to create through other means, such as through use of counters. For e.g., the FPGA may have a 50MHz clock input but you actually need a 143MHz clock so in this case it makes sense to use a PLL to generate the 143MHz clock (or any other speed including lower speeds than 50MHz). PLLs are clever units but are not perfect so you may not be able to get the exact speed you require but often can get very close so it doesn't make too much of a difference. Also note that an FPGA will have a specific number of PLL units so it's important that you check how many your FPGA has to see if it meets your design requirements.

Please see the following video for an introduction to PLLs:

For a specific example of adding a PLL to a design using Quartus please see:

Quartus SignalTap II Logic Analyzer

With traditional digital electronics including computer systems a designer would typically check that the various signals are behaving as they should by using a multimeter, oscilloscope, logic analyzer or even all three. SignalTap simulates a logic analyzer by using the logic and memory blocks available in your FPGA without the need to connect an external logic analyzer and also has the advantage that signals can be analyzed without routing them to available I/O pins that may otherwise be needed. SignalTap works through the JTAG connection of your FPGA board which is usually what's also used to configure the board so it's very convenient.

You should be aware, however, that because SignalTap takes up logic elements of your FPGA that you may have otherwise needed for your design and will not work with CPLDs ( Complex Programmable Logic Device) due to not having enough resources available. Another issue is that SignalTap can only perform a functional debug; any timing delays inherent in the design will not appear in the captured data as data is only sampled on the rising edge of the sampling clock, hiding information that may occur at other points in the clock cycle.

The more channels and complexity of trigger conditions that you add the more logic elements are needed in your FPGA and the greater number of channels and sample depth the more memory blocks are needed. Although SignalTap is limited to a very generous 2048 channels at 128K samples per channel it's unlikely you'll reach this limit due to the resources it would require from your FPGA.

SignalTap allows up to 10 sequential/non-sequential trigger conditions to be monitored. and the resources needed are displayed in the Instance Manager of SignalTap.

For an introduction to using the SignalTap II logic analyzer, of which the information in this section is based on, please see the video that follows:

I will now go through an example of setting up SignalTap which assumes you already have created a functional design for your FPGA and that you have at least run Analysis & Synthesis (Processing->Start->Start Analysis & Synthesis), and that you have your FPGA board connected to your PC and powered on.

First:

Tools->SignalTap II Logic Analyzer

In the node area in the Setup tab (which should be selected by default) double-click the white space Node Finder window (see image below). It is recommended from the Filter drop-down to either select SignalTap II: pre-synthesis, which effectively gives you the nodes straight from your design and appear in black, or SignalTap II: post-fitting, which are the nodes available after optimizations and appear in blue. Click the List button to show the nodes.

In the Matching Nodes section find the GPIO to add (you can expand buses to get to the individual I/O) and click the '>' (Copy to Selected Nodes) button for each I/O you want to add and it will appear in the Nodes Found box. Click the Insert button followed by the Close button and you will see in the main logic analyzer window (below) that the I/O you selected has been added. There are a number of actions you can perform on the nodes such as to right-click and select Delete to remove the signal. You can also group signals together by selecting them with Ctrl + left-click and then right-click and select Group.

You will also need to add a signal to be used as a clock to set the sample rate; in the Signal Configuration section click the '...' button to the right of the 'Clock' box and use the Node Finder window as before to add a clock signal.

With the nodes added you can use the Data Enable and Trigger Enable check boxes to determine if a signal is to be monitored and whether to be used as a trigger as well as set the trigger conditions using the drop-down.

If you make any changes to SignalTap, such as to add or remove nodes, you will need to compile the project again and program the FPGA with the updated design. Unfortunately only the subscription version of Quartus provides the rapid recompile option which would speed up the process.

When you are happy with the setup save the configuration using File->Save  and after saving you will be asked if you want to enable the SignalTap file for the current project: click the yes button.  To enable or specify a different SignalTap (.stp) file: Assigments->Settings... Click 'SignalTap II Logic Analyzer' in the Category section. Check/uncheck 'Enable SignalTap II Logic Analyzer' to enable/disable the SignalTap file which is specified in the 'SignalTap II File name:' box.

Next you will need to compile your project, Processing->Start Compilation, which will add the required logic to your design for the SignalTap logic analyzer and provided there are no errors you need to program your FPGA board: Tools->Programmer.

Once programmed, return to the SignalTap window and wait for the Instance Manager (top left under the toolbar) changes to 'Ready to acquire'.

In the Instance Manager section there are 4 buttons, Run Analysis, Autorun Analysis, Stop Analysis and Read Data, and they do the following:

Run Analysis: starts the monitoring until trigger event occurs or logic analyzer is stopped.

Autorun Analysis: automatically reruns the logic analyzer after trigger conditions satisifed and a capture has been performed, continually updating the display.

Stop Analysis: stops the logic analyzer from looking for trigger conditions and displays the captured data.

Read Data: transfers data currently stored in the FPGA capture buffer to the display and is to be used if the data for some reason isn't automatically transferred.

Click the 'Run Analysis' button and you should see captured data like as follows:

When you hover over the waveform the cursor will change to a zoom in tool; left-click to zoom in and right-click to zoom out.

Everything in the waveform display is referenced to the master time bar indicated with a thick black line. Use the previous/next transition blue arrows to move the master time bar which will update the Value column showing the logical state of the waveform where the master time bar is as well as the value range of the master time bar. Reference time bars can be added, which is useful for measuring the time between events, for e.g. To add a time bar, right-click the samples bar (where the cursor changes to a hand) and select Insert Time Bar... Enter samples/time value of where the bar is to be placed and click OK. The value above the bar will be displayed in relation to the master time bar so that, for e.g., if the master time bar is at 0 and a time bar is placed at 50ns it will display 50ns but if you move the master time bar to 10ns the bar you added will now show +40ns.

To delete a time bar right-click it where its sample/time value is displayed (the cursor will change into double-ended arrow which also lets you move the time bar left/right if dragged), right-click and select Delete Time Bar. There is also the option to delete all time bars, set as master time bar and to move master time bar. Another useful feature is to right-click and select Insert Master Time Bar which will place the master time bar at the clicked point and make the existing master time bar a reference time bar.

An example below shows captured waveforms along with a number of time bars:

Another video to help with using SignalTap, which shows a practical example can be seen as follows: