Short Courses
  • Design of digital SoC for digital signal processing using FPGA: IDEC, KAIST (02/2017)
This short course introduces the design and optimization of digital SoC for digital signal processing applications, which includes hardware-softeware partitioning, on-chip communication and hardware-softeware optimization. The design lab includes the hardware and software implementation of fast Fourier transform (FFT) on Xilinx FPGA, ZYNQ.

  • High-level design and verification of digital SoC: IDEC, Kwangwoon University (08/2014)
This short course deals with high-level design and verification of digital SoC, focusing on computation-intensive systems. The proposed design flow is mainly characterized by the architecture exploration on a high level. In more detail, based on the cycle-accurate model and bit-accurate model of the system written in C++, the resulting performance and complexity metrics are evaluated in the early stage of design flow. For example, the performance metrics such as quantization error and overflow can be evaluated based on the high-level models. The design lab shows that the rough estimate of complexity metrics such as area and speed is carried out based on the high-level models.
  • Design of high-performance SoC for digital signal processing applications: IDEC, KAIST (07/2014)
This short course deals with the SoC design for digital signal processing applications. The performance and complexity metrics are introduced and the corresponding trade-offs are explained. The proposed design flow ranges from system specifications to algorithm-level design, architecture-level design and logic-level design. The design flow is exemplified with two digital signal processing algorithms - infinite impulse response (IIR) filter and fast Fourier transform (FFT) processor. The design lab consists of functional simulations (C++), cycle-accurate simulations (C++), bit-accurate simulations (C++), logic simulations (VerilogHDL) and logic synthesis (Design Compiler).
    • Multi-band multi-channel terminal SoC for cellular networks, Radio Research Center, Kwangwoon Univ. (01/2018)

      In this talk, we introduce the design and implementation of multi-mode multi-channel system-on-a-chip (SoC) for mobile communications. The designed transceiver SoC consists of sample rate conversion, channel selection and digital compensation, and supports both WCDMA (3G) and LTE (4G) standards. The entire design procedure ranging from system design down to register transfer level (RTL) design is introduced, for example, showing how to evaluate the fixed-point performance early in the design procedure. The architectures of key building blocks are briefly explained, which include digital filter, fast Fourier transform (FFT) and coordinate digital computer (CORDIC), focusing on the corresponding performance-complexity trade-off.

    • Application-specific design approaches for signal processing applications: CECS, UC Irvine (08/2017)

      The application-specific design for signal processing applications tends to necessitate multi-disciplinary knowledge on system, algorithm, architecture and circuit levels. In this talk, we will introduce our application-specific design approaches for various signal processing applications. In addition, we discuss several design challenges involved in system-on-a-chip (SoC) design for neural networks, regarding how to cusmomize the on-chip bus architecture.

      • Undergraduate seminar series: overview of SoC design, Konkuk University (05/2016)

        The demand for good SoC designers seems to be everlasting since it enables us to implement any emerging technologies (e.g., IoT, artificial intelligence). The paradigm shift toward S/W-centric design does not imply that H/W becomes less important. Rather the knowledge of H/W becomes more crucial, e.g., that of
        computer architecture. In addition to optimized H/W or S/W design, the optimized on-chip communication becomes a key to the successful SoC design. Hands-on programming (e.g., C/C++) and implementation experiences (e.g., FPGA) are must-haves in the SoC era. Various domain knowledge (e.g., image processing) and mathematics are an absolute plus, in particular for the leaders of a cross-disciplinary team.

      • Design challenges of milimeter wave phased antenna array: LG Electronics (04/2016)

        Milimeter wave communication is emerging as a promising physical layer technology for 5G communications. Phased antenna array helps to overcome increased signal attenuation in mmW. Antenna gain and nulling capability are highly dependent on array configuration (e.g., antenna selection). RF/LO phase shift (possibly assisted by digital one) seems to be a reasonable RX architecture. Phase shift selection tends to rely on training-based sector search (plus feedback) Sector search space should consider channel & interference condition and phase error. Digital calibration of phase error (and possibly IQ imbalance) may be critical from the perspective of beamforming gain.

      • Advanced link adaptation algorithms for WiFi: LG Electronics (02/2015)

        Link adaptation is an adaptive way of determining a variety of system parameters such as a Modulation and Coding Scheme (MCS) and a transmit beamforming matrix that suit the given channel condition best. Link adaptation is a key element of a WiFi PHY/MAC system in that its performance (e.g., goodput or energy efficiency) heavily depends on how link adaptation is carried out. The MCS selection is largely categorized into two approaches: ACK-based approach and preamble-based approach. ACK-based approach (e.g., Automatic Rate Fallback (ARF) from Lucent Bell Lab.) simply counts the number of successive successes/failures of data transmissions and increases/decreases the MCS accordingly, whereas preamble-based approach (e.g., Exponential effective SNR mapping (EESM) from Ericsson) measures the SNR based on the received preamble and maps it into the throughput-maximizing MCS.

      • Digital frontend architecture for multiband multimode cellular radios: LG Electronics (01/2014)

        Digital FrontEnd (DFE) resides between RF/analog transceiver and digital baseband modem. The major roles of DFE include channel selection, sample rate conversion and impairment compensation. Digital up/down conversion may be used to support multi-carrier transmission/reception such as multi-carrier WCDMA and carrier aggregation (LTE-Advanced). DFE involes prohibitively high computational complexity and its operating frequency is generally much higher than that of digital baseband modem. Many sophisticated signal processing algorithms and architectures are useful to the successful implementation of DFE, for example, polynomial interpolation (e.g., Farrow interpolation), reconfigurable digital FIR filtering (e.g., Constant Shift Method (CSM)), COordinate Rotation DIgital Computer (CORDIC). Impairment compensation includes IQ mismatch correction and DC offset correction.

      • Carrier aggregation for LTE-Advanced: Design challenges of terminals, RF IC Tech. Workshop (09/2013)

        Carrier aggregation is a key feature of 3GPP LTE that addresses the support of higher data rates and utilization of fragmented spectrum
        holdings. In this talk, the relevant design challenges of terminals are discussed. The transmitter architectures are reviewed, and the minimum amount of power amplifier back-offs is evaluated. In addition, several receiver architectures are compared from the perspective of design tradeoff. The radio impairments affecting the receiver performance are analyzed and the simulation results are provided.