Research Areas

Thanks to continuously growing CMOS technology, today's SoCs often include many sophisticated signal processing algorithms, e.g., in order to compensate for the imperfection of analog circuitry or ease the technology migration. Cross-level design exploration and optimization are critial to successful design of an SoC for signal processing algorithms. Two key design levels involved are the algorithm and architecture levels.  The trade-off of performance and complexity (shown below) is most influenced by the algorithmic and architectural  design exploration and optimization.

Our research interests are focused on designing and optimizing an SoC for diverse computation-intensive signal processing algorithms where both algorithmic and architectural design space exploration is crucial to the performance and complexity. The target applications include machine learning, cognitive radios, software-defined radios and compressed sensing. 

The example signal processing algorithms include Fast Fourier Transform (FFT), convolutional neural network (CNN) and orthogonal matching pursuit (OMP). The following figure summarizes the portfolio of SoC IPs that we have developed so far. Each of the SoC IPs was designed and optimized based on the proprietary design space exploration, which is illustrated next.



In order to cope with every increasing design complexity, platfform-based SoC design emerges as the most promising solution. Given a well-designed SoC platform, the success of SoC design mostly hinges on proper partitioning of system functions between HW and SW. Once each system function is assigned to either HW or SW, the remaining design task is split between HW and SW until the final netlist and execution code are obtained. Depending on whether the design meet the system specification or not, it may be necessary to repeat the HW-SW partitioining several times. Some of the key design parameters that are optimized in the design space exploration are listed below. We are currently focusing on designing and optimizing an SoC for machine learning, e.g., convolutional neural network (CNN), in particular, focusing on the on-chip communication architectures and instruction set architecture (ISA).