Projects

On-going Projects

It is predicted that IoT devices will be able to support not only high-rate networking but gesture/activity sensing in the near future. Centered on IEEE 802.11be and IEEE 802.11bf, the standardizations of communication-sensing convergence IoT devices are expected to be finalized in 2024. Channel state information (CSI) processing is considered as one of the key technologies for the communication-sensing convergence IoT devices, which is set to be the main theme of this project. The proposed CSI processing consists of time-frequency synchronization, channel coefficient estimation,  CSI feedback generation, statistical information extraction and sensing. More specifically, the proposed CSI processing is characterized by statistical information based channel coefficient estimation, opportunistic channel sounding and DNN-based gesture/activity sensing. In addition, in order to make the algorithm-architecture co-design more effective, we propose a push-button style agile SoC design methodology using SystemC-TLM (Transaction-Level Modeling) based virtual platform simulators. An in-house accelerator simulator is developed to optimize hardware-software partitioning and on-chip memory-network design and leverage the efficacy of the state-of-the-art EDA tools (e.g., Mentor's Catapult HLS and Synopsys ASIP Designer).

Compute-in-Memory (CiM) is currently considered as an attractive IP block that makes it possible to achieve high energy efficiency. The relevant memory compiler has a potential to facillitate the integration of CiM into an SoC although the commercial availability has not been comparable to its counterpart of traditional on-chip memory yet. In this project, a virtual platform simulator is developed to help guide the decision of which design parameters the memory compiler should support (e.g., the width, depth and aspect ratio etc.). In order to evaluate the performance impact of the design parameters, the proposed virtual platform simulator includes a SystemC-TLM based cycle-accurate model of CiM circuitry based on volatile/non-volatile memory. Furthermore, the proposed simulator is capable of evaluating the performance/power impact of inter-/intra accelerator dataflow. Using the simulator, the local memory manager and network-on-chip (NoC) of a CiM accelerator are optimized so as to maximize the perforamance and/or minimize the power consumtion. The proposed simulator is designed to be plugged into Synopsys's Platform Architect, which makes it possible to utilize the extensive set of simulation models such as AMBA AXI bus interconnect and DRAM/SRAM.

Compute-in-Memory (CiM) emerges as one of the key enablers of accelerator-centric SoCs and it is shown that the use of CiM can improve the power efficiency of hardware accelerators significantly. The proposed virtual platform simulator includes a  SystemC-TLM based cycle-accurate model of eFlash-based CiM circuitry, which helps to estimate the performance impact of CiM circuit parameters, for example, the array dimension, the number of bits/cell etc. Moreover, in order to fully exploit the advantages of CiM, we propose a new SoC interface architecture that includes the local memory, bus interface and DMA controller. The proposed simulator is designed to be plugged into Synopsys's Platform Architect, which makes it possible to utilize the extensive set of simulation models such as AMBA AXI bus interconnect and DRAM/SRAM.

The design of a system-on-chip (SoC) for digital signal processing applications heavily relies on a few design decisions such as hardware-software partitioning and on-chip network optimization. In this project, we newly develope an efficient design procedure where the aforementioned design decisions are carefully handled. The use of high-level design tools such as SystemC based transaction-level modeling (TLM) will be closely investigated. The design procedure devised in this project will be applied to the design of emerging technologies such as neural network platforms, compressed sensing and software-defined radios.

Completed Projects

Recently a lot of attention has been paid to Ferroelectric Nonvolatile FET (FeFET) based CMOS circuitry. In this project, a virtual platform simulator is proposed to evaluate the performance and power consumption of FeFET based SoC. In particular, the power saving of FeFET based CNN accelerator, which replaces the conventional arithmetic units (adder and multipliers) by the FeFET based circuits is predicted by the pre-RTL SoC simulator.

The dataflow of hardware accelerator has a great impact on the performance and energy efficiency. Therefore, it is of significant importance to simulate and optimize a dataflow early in the design, e.g., without going through RTL coding. The proposed design framework consists of a software tool (written in SystemC-TLM) for simulations and optimizations and a template hardware model (written in VerilogHDL) for implementations. The software tool again consists of S-DDG simulator and full-system simulator. The S-DDG simulator uses the S-DDG to simulate and optimize the dataflow inside accelerator. On the other hand, the full-system simulator, which is a virtual platform simulator, uses the cycle-accurate modeling to evaluate the performance and energy consumption taking into account the dataflow outside accelerator.

The selection of Modulation and Coding Scheme (MCS) that suit the given channel condition best, the so-called link adaptation, is a key element of high throughput communication networks such as 4G LTE and WiFi in that its performance (e.g., goodput or energy efficiency) heavily depends on how link adaptation is carried out. In this project, we firstly develop the neural network based link adaptation algorithm and its on-chip network for the system-on-chip implementation. Firstly, the architecture and parameters of the neural network are derived based on the simulation results, a training method with self-generated training data is newly proposed, and the throughput is measured over the air. Secondly, based on the design space exploration using the transaction-level model simulator, the topology and protocol of the on-chip network for the neural network are optimized in terms of processing speed and power consumption. Also the architecture of the hardware accelerator capable of parallel processing is designed. Lastly, the proposed algorithm and on-chip network are optimized further and verified using the proprietary prototype system consisting of modem and neural network.

Blind wideband sampling is one of the break-through sub-sampling techniques that enables the sub-Nyquist sampling of a wideband sparse signal without knowing the frequency location of constituent narrowband signals. Blind wideband sampling consists of Modulated Wideband Converter (MWC) and reconfigurable multi-band channelier. The latter first estimates the frequency location of the constituent narrowband signals and then hand them over to the following functional block, e.g, digital baseband receiver. Compressed sensing has emerged as a promising signal processing algorithm since it has a broad range of applications in wireless communications (e.g., massive MIMO) and biomedical imaging (e.g., ultra-sound imaging). Academia has recently made a lot of research effort to devise efficient SoC architectures for compressed sensing. In this project, orthogonal matching pursuit (OMP), one of the well-known compressed sensing algorithm, is implemented on commercially available FPGA (Xilinx ZYNQ 7020). The focus is given to the design space exploration for the hardware-software partitioning and on-chip communication architectures, which is facilitated by the use of transaction level model (TLM) based on the so-called communication analysis graph (CAG).

Digital FrontEnd (DFE) resides between RF/analog transceiver and digital baseband modem. In more detail, its transmitter part follows the digital baseband transmitter and precedes the Digital-to-Analog Converter (DAC), whereas its receiver part follows the Analog-to-Digital Converter (ADC) and precedes the digital baseband receiver. The major roles of DFE include channel selection, sample rate conversion and impairment compensation. Digital up/down conversion may be used to support multi-carrier transmission/reception such as multi-carrier WCDMA and carrier aggregation (LTE-Advanced). It should be noted that DFE involes prohibitively high computational complexity and its operating frequency is generally much higher than that of digital baseband modem. Many sophisticated signal processing algorithms and architectures are useful to the successful implementation of DFE, for example, polynomial interpolation (e.g., Farrow interpolation), reconfigurable digital FIR filtering (e.g., Constant Shift Method (CSM)), COordinate Rotation DIgital Computer (CORDIC).

The selection of Modulation and Coding Scheme (MCS) that suit the given channel condition best, the so-called link adaptation, is a key element of a WiFi PHY/MAC system in that its performance (e.g., goodput or energy efficiency) heavily depends on how link adaptation is carried out. It is largely categorized into two approaches: ACK-based approach and preamble-based approach. ACK-based approach (e.g., Automatic Rate Fallback (ARF) from Lucent Bell Lab.) simply counts the number of successive successes/failures of data transmissions and increases/decreases the MCS accordingly, whereas preamble-based approach (e.g., Exponential effective SNR mapping (EESM) from Ericsson) measures the SNR based on the received preamble and maps it into the throughput-maximizing MCS.