MPEG-4 Part II Video Coding

  • MPEG-4 Part II video coding
  1. Shape adaptive DCT
    • H. C. Hsu, et al., "Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding," IEEE Transactions on Circuits and Systems for Video Technology,, vol. 18, pp. 375-386, March 2008.
    • H.-C. Hsu, et al., "An MPEG-4 shape-adaptive inverse DCT with zero skipping and auto-aligned transpose memory," in APCCAS, Tainan, Taiwan, 2004, pp. 773-776.
  2. Motion estimation
    • E. A. Al_Qaralleh, et al., "An Efficient Binary Motion Estimation Algorithm and its Architecture for MPEG-4 Shape Encoding," IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, pp. 859-868, July 2006.
    • E. A. A. Qaralleh and T. S. Chang, "Fast Variable Block Size Motion Estimation by Adaptive Early Termination," IEEE Transactions on Circuits and Systems for Video Technology,, vol. 16, pp. 1021-1026, August 2006.
    • C. C. Lin, et al., "A Fast Algorithm and its Architecture for Motion Estimation in MPEG-4," in APCCAS, 2006.
    • H.-Y. Chin, et al., "A bandwidth efficient subsampling-based block matching architecture for motion estimation," in ASPDAC, 2005, pp. D/7-D/8 Vol. 2.
    • E. A. Al_Qaralleh and T.-S. Chang, "Fast Motion Estimation by Adaptive Early Termination," in SiPS, 2005, pp. 678-681.
    • C. C. Lin, et al., "Hardware oriented algorithms for motion estimation in MPEG-4 AVC/H.264 Video coding," in VLSICAD, 2006.
  3. Texture encoder
    • H.-C. Hsu, et al., "Architecture design of MPEG-4 texture decoder supporting object-based video coding," in VLSI-TSA, 2005, pp. 275-278.
    • H. C. Hsu, et al., "An energy efficient MPEG-4 texture decoder " in VLSICAD, 2004.
  • Digital signal processing block
  1. Distributed arithmetic design
    • H. C. Chen, et al., "Distributed arithmetic realization of cyclic convolution and its dft application," Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems], pp. 615-629, 2005.
    • H.-C. Chen, et al., "A memory-efficient realization of cyclic convolution and its application to discrete cosine transform," IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, pp. 445-453, March 2005.
    • H.-C. Chen, et al., "The long length DHT design with a new hardware efficient distributed arithmetic approach and cyclic preserving partitioning," IEICE Transactions on Electronics, vol. E88, pp. 1061-1069, May 2005.
    • H.-C. Chen, et al., "A low power and memory efficient distributed arithmetic design and its DCT application," in APCCAS, Tainan, Taiwan, 2004, pp. 805-808.
  2. Filter design
    • T. S. Chang and C. W. Jen, "Hardware-efficient pipelined programmable FIR filter design," Computers and Digital Techniques, IEE Proceedings-, vol. 148, pp. 227-232, 2001.
    • T.-S. Chang, et al., "Low-power FIR filter realization with differential coefficients and inputs," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 137-145, Feb. 2000.
    • T.-S. Chang and C.-W. Jen, "Low power FIR filter realization with differential coefficients and input," in ICASSP, Seattle, WA, USA, 1998, pp. 3009-3011.
  3. Design with subexpression sharing
    • T.-S. Chang, et al., "Hardware-efficient DFT designs with cyclic convolution and subexpression sharing," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 886-892, Sep. 2000.
    • T.-S. Chang and C.-W. Jen, "Hardware efficient transform designs with cyclic formulation and subexpression sharing," in ISCAS, Monterey, CA, USA, 1998, pp. 398-401.
  • RSA design
    • C.-C. Yang, et al., "New RSA cryptosystem hardware design based on Montgomery's algorithm," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, pp. 908-913, July 1998.
    • C.-C. Yang, et al., "IC design of a high speed RSA processor," in APCCAS, Seoul, South Korea, 1996, pp. 33-36.
  • Other designs
    • T. S. Chang and C. W. Jen, "On-chip memory module designs for video-signal processing," Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems], vol. 144, pp. 138-144, 1997.
    • C. W. Jen and T. S. Chang, "Concurrent line access of on-chip memory," R. O. C. Patent 267221 1996/01/01, 1996.
    • T.-S. Chang and C.-W. Jen, "Embedded memory module design for video signal processing," in IEEE Workshop on VLSI Signal Processing, Osaka, Jpn, 1995, pp. 501-510.
    • C.-M. Huang, et al., "Multiplierless reconfigurable resizer for multi-window image display," IEEE Transactions on Consumer Electronics, vol. 43, pp. 826-832, 1997.
    • C.-M. Huang, et al., "Multiplierless reconfigurable resizer for multi-window image display," in IEEE International Conference on Consumer Electronics, Rosemont, IL, USA, 1997, pp. 402-403.