Research

Short Bio

Monica Magalhães Pereira received her Bachelor degree in Computer Science at Universidade Federal do Rio Grande do Norte, Natal/Brazil in 2005. She received a M.Sc. in 2008 also in Computer Science from Universidade Federal do Rio Grande do Norte and Ph.D. degree at Universidade Federal do Rio Grande do Sul, Porto Alegre/Brazil in 2012. In 2010 she was in a doctoral internship at Karlsruhe Institute of Technology, Karlsruhe/Germany. She is currently an Associate Professor at UFRN, where she is chair of Systems-on-Chip Laboratory (Laboratório de Sistemas em Chip - LASIC). She has experience in Computer Science with emphasis in Computer Systems Architecture, working with the topics: embedded systems, fault tolerance, reconfigurable architectures, multicore architectures and network-on-chip. Since 2017, she is chair of IEEE Women in Engineering group at UFRN.

Main Publications


PEREIRA, M. M. (2012). A Reliability Analysis Approach to Assist the Design of Aggressively Scaled Reconfigurable Architectures (Doctoral dissertation). PhD Dissertation


Journals

  1. LOPES, ALBA ; PEREIRA, M. M. Fast DSE of reconfigurable accelerator systems via ensemble machine learning. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v. 1, p. 1-15, 2021.

  2. LOPES, ALBA SANDYRA BEZERRA ; PEREIRA, M. M. Aceleradores Reconfiguráveis no Projeto Multicore: uma análise de custo versus benefício. HOLOS (NATAL. ONLINE), 2020. (in press)

  3. SILVA, JEFFERSON ; MAIA, S. M. D. M. ; PEREIRA, M. M. ; KREUTZ, M. E. . A comparison between evolutionary and local search techniques applied to NoC Design Space Exploration. International Journal of Innovative Computing and Applications (Online), 2020. (in press)

  4. LOPES, ALBA S. B. ; PEREIRA, M. M . Exploração de espaço de projeto para multicores heterogêneos com o uso aprendizado de máquina: o estado da arte. Brazilian Journal of Development, v. 6, p. 26730-26749, 2020.

  5. SILVA, J. ; MAIA, S. M. D. M. ; PEREIRA, M. M. ; KREUTZ, M. E. . A comparison between evolutionary and local search techniques applied to NoC Design Space Exploration. International Journal of Innovative Computing and Applications (Online), 2020.

  6. FERREIRA, R. ; BUENO, C. ; LAURE, M. ; PEREIRA, M. M.; Carro, L. A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design. Transactions on High-Performance Embedded Architectures and Compilers, v. 5, p. 121-139, 2019.

  7. SILVA, J.; KREUTZ, M.; PEREIRA, M. M. ; COSTA-ABREU, M.. An investigation of latency prediction for NoC-based communication architectures using machine learning techniques. JOURNAL OF SUPERCOMPUTING, v. 1, p. 1-19, 2019.

  8. FERREIRA, R.; DENVER, W.; PEREIRA, M. M. ; WONG, S.; LISBOA, C; A. ; CARRO, L. A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY (ONLINE), v. 85, p. 45-66, 2015.

  9. PEREIRA, M. M.; CARRO, L . Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates. International Journal of Reconfigurable Computing (Print), v. 2011, p. 1-17, 2011.


Book Chapters

1. BECK FILHO, A. C. S. ; LISBOA, C. A. L. ; CARRO, L. ; NAZAR, G. L. ; PEREIRA, M. M. ; Ferreira, R. R. . Adaptability: The Key for Future Embedded Systems. In: Antonio Carlos Schneider Beck; Carlos Arthur Lang Lisbôa; Luigi Carro. (Org.). Adaptable Embedded Systems. 1ed.New York: Springer, 2012, v. , p. 1-12.

2. BECK FILHO, A. C. S. ; PEREIRA, M. M. Reconfigurable Systems. In: Antonio Carlos Schneider Beck; Carlos Arthur Lang Lisbôa; Luigi Carro. (Org.). Adaptable Embedded Systems. 1ed.New York: Springer, 2012, v. , p. 41-94.

3. PEREIRA, M. M.; RHOD, E. L. ; CARRO, L Fault Tolerant Design and Adaptability. In: Antonio Carlos Schneider Beck; Carlos Arthur Lang Lisbôa; Luigi Carro. (Org.). Adaptable Embedded Systems. 1ed.New York: Springer, 2012, v. , p. 211-242.


Conferences

  1. CARDOSO, E. B. G. ; AVELINO, A. A. F. ; KREUTZ, M. E. ; PEREIRA, M. M. Redes em Chip Irregulares para Tolerância a Falhas e Atendimento de Tempo Real. In: IBERCHIP Workshop 2021, 2021, Lima. Proceedings of IBERCHIP Workshop 2021, 2021.

  2. SILVA, R. S. ; KOROL, G. ; JORDAN, M. ; BRANDALERO, M. ; Hübner, M. ; PEREIRA, MONICA MAGALHAES ; Rutzig, M. B. ; BECK FILHO, A. C. S. . A Management Technique for Concurrent Access to a Reconfigurable Accelerator. In: 33ʳᵈ Symposium on Integrated Circuits and Systems Design (SBCCI), 2020, Virtual. Proceedings of 33ʳᵈ Symposium on Integrated Circuits and Systems Design, 2020.

  3. LOPES, A. S. B. ; PEREIRA, MONICA MAGALHAES . A Machine Learning Approach to Accelerating DSE of Reconfigurable Accelerator Systems. In: 33ʳᵈ Symposium on Integrated Circuits and Systems Design (SBCCI), 2020, Virtual. Proceedings of 33ʳᵈ Symposium on Integrated Circuits and Systems Design, 2020.

  4. LOPES, A. S. B. ; BECK FILHO, A. C. S. ; BRANDALERO, M. ; PEREIRA, M. M. Generating Optimized Multicore Accelerator Architectures. In: IX Brazilian Symposium on Computing Systems Engineering, 2019, Natal. Proceedings of IX Brazilian Symposium on Computing Systems Engineering, 2019.

  5. SILVA, R. S. ; CRUZ, P. P. ; KREUTZ, M. E. ; PEREIRA, M. M. Communication Latency Evaluation on a Software-Defined Network-on-Chip. In: IX Brazilian Symposium on Computing Systems Engineering, 2019, Natal. Proceedings of IX Brazilian Symposium on Computing Systems Engineering, 2019.

  6. BEZERRA, G. A. ; CRUZ, P. P. ; KREUTZ, M. E. ; PEREIRA, M. M. Generation of Application Specific Fault Tolerant Irregular NoC Topologies Using Tabu Search. In: IX Brazilian Symposium on Computing Systems Engineering, 2019, Natal. Proceedings of IX Brazilian Symposium on Computing Systems Engineering, 2019.

  7. COSTA-ABREU, M. C. ; PEREIRA, M. M. Women in Resistance: Reporting the impact of IEEE WiE UFRN. In: 13º Women in Information Technology (CSBC), 2019, Belém. 13º Women in Information Technology (CSBC), 2019.

  8. KOROL, G. ; JORDAN, M. ; SILVA, R. S. ; PEREIRA, M. M. ; BRANDALERO, M. ; Rutzig, M. B. ; BECK FILHO, A. C. S. . A Runtime Power-Aware Phase Predictor for CGRAs. In: 2019 International Conference on Reconfigurable Computing and FPGAs, 2019, Cancun. Proceedings of 2019 International Conference on Reconfigurable Computing and FPGAs, 2019.

  9. ERICHSEN, A. G. ; SARTOR, A. L. ; SOUZA, J. ; PEREIRA, M. M. ; WONG, STEPHAN ; BECK FILHO, A. C. S. . ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores. In: The 14th International Symposium on Applied Reconfigurable Computing, Santorino, 2018.

  10. LOPES, A. S. B. ; SANTOS, E. V. ; KREUTZ, M. E. ; PEREIRA, M. M. A Runtime Mapping Algorithm to Tolerate Permanent Faults in a CGRA. In: VI Brazilian Symposium on Computing Systems Engineering, João Pessoa, 2016.

  11. MESQUISA, J. W. ; CRUZ, M. O. ; KREUTZ, M. E. ; PEREIRA, M. M. Design Space Exploration using UTNoCs and Genetic Algorithm. In: VI Brazilian Symposium on Computing Systems Engineering, João Pessoa, 2016.

  12. LOPES, A. S. B. ; KREUTZ, M. E. ; PEREIRA, M. M. Enabling NoC Performance Improvement using a Fault Tolerance Mechanism. In: V Brazilian Symposium on Computing Systems Engineering, Foz do Iguaçu, 2015.

  13. Ferreira, D. ; PEREIRA, M. M. . A Transparent Fault Tolerance Solution for NoCs: A Reliability Analysis. In: Iberchip XX Workshop, Santiago, 2014, .

  14. FERREIRA, R. ; MEIRELLES, W. ; PEREIRA, M. M. ; WONG, S. ; QUADROS, J. ; CARRO, L . A Run-Time Modulo Scheduling by using a Binary Translation Mechanism. In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos Island, 2014.

  15. FERREIRA, R. ; DUARTE, V. ; MEIRELES, W. ; PEREIRA, M. M. ; CARRO, L ; WONG, S. . A Just-In-Time Modulo Scheduling for Virtual Coarse-Grained Reconfigurable Architectures. In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos Island, 2013.

  16. PEREIRA, M. M.; CARRO, L. Using a Reliability Analysis to Design Low Cost Reliable-Aware Coarse-Grained Reconfigurable Architectures. In: 4th Workshop on Design for Reliability (DFR 2012), Paris, 2012.

  17. PEREIRA, M. M.; BRAUN, LARS ; HUBNER, MICHAEL ; BECKER, JURGEN ; CARRO, L. Run-time resource instantiation for fault tolerance in FPGAs. In: 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), San Diego. 2011.

  18. FERREIRA, R. ; Julio Goldner Vendramini ; Lucas Mucida ; PEREIRA, M. M. ; CARRO, L . An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture. In: Embedded Systems Week (ESWeek'11), 2011, Taipei. CASES '11. New York: ACM, 2011.

  19. FERREIRA, R. ; BUENO, C. ; LAURE, M. ; PEREIRA, M. M. ; CARRO, L . A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design. In: 4th HiPEAC Workshop on Reconfigurable Computing, 2010, Pisa, p. 7-16, 2010.

  20. PEREIRA, M. M.; CARRO, Luigi . Dynamic Reconfigurable Computing: the Alternative to Homogeneous Multicores under Massive Defect Rates. In: 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC'10, Karlsruhe, 2010.

  21. PEREIRA, M. M.; LO, T. B. ; CARRO, L . A Self-adaptive Approach for Fault-Tolerance in Future Technologies. In: The 1st HiPEAC Workshop on Design for Reliability (DFR'09), 2009, Paphos. The 1st HiPEAC Workshop on Design for Reliability (DFR'09), 2009.

  22. PEREIRA, M. M.; CARRO, L . Dynamically Adapted Low-Energy Fault Tolerant Processors. In: NASA/ESA Conference on Adaptive Hardware and Systems, San Francisco, 2009.

  23. PEREIRA, M. M.; CARRO, L . A Self-Adaptive Approach to Increase Reliability of Processors. In: 17th IFIP/IEEE International Conference On Very Large Scale Integration (VLSI-SoC'09), Florianópolis, 2009.