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Passive Thermal Management using Phase Change Materials

PI: Dr. Amy Marconnet , Dr John Howarter                                                                                                                         
The contributions of my colleagues during this project - Alex Bruce , Zhenhuan Xu, Javieradrian Ruiz, Prahlad Kulkarni, Michael Woodworth and Claire Lang are gratefully acknowledged)
For a Short Summary - Click here
Thesis - Click here

Increasing power dissipation in processors and decreasing feature sizes. Power dissipation in handheld devices has increased manifold whereas thermal limits in a mobile device, such as case, processor and battery temperature, remain unchanged, thus creating a thermal bottleneck. Increased demand for responsiveness leads to an increase in device temperature. 
Traditional thermal design is based on worst case scenario - minimizing thermal resistances. Latent heat energy storage systems use the latent heat of a material to limit temperatures. Phase Change materials (PCM's) have found applications in textiles , passive storage in buildings and solar power plants. Exploiting thermal capacitance - using sensible heat - to absorb heat and then dissipate heat over long time periods is a promising alternative. 
We explore the feasibility of using PCM's in mobile devices to increase their operating time under peak power conditions. Computational models are developed at the system and board level to understand the impact of the PCM on the processor temperature and identify the ideal material properties of the PCM. Thermal testing is done using a development board which runs an Android operating system to mimic real time use cases.

Latent heat energy storage response to power spikes

Thermal Characterization
A thermal property testing rig based on reference bar method (ASTM D5470) to measure thermal resistance (designed and constructed in-house). Infra-Red Microscope is used as a non-contact method for determining temperature. 
More details are in paper (click here) published at ASME InterPack Conference, July 2015.


            Thermal Property Test Rig (TPTR)                                                               Cross section view of TPTR                                                                 Line graph of temperature profile
                                                                                                                                                                                                                                                        in Reference - Sample - Reference stack
                                                                                                                                                                                                                                                      (Sample bound by two dashed black lines)
In-Situ thermal testing

Single Board computer  (SBC) by Inforce Computing is used for package level testing under real usage conditions.  Single Board computer (SBC) is a development board consisting of essential components in a mobile device – processor, GPU and networking capabilities with pre-loaded Android OS

The temperatures of top surface of die,enclosure and PCM are measured using an Infra-red microscope.  The tests are performed in a bottom-up sequence - die , die + enclosure , die + enclosure + PCM for comparison. Commercial PCMs are used for different enclosures made of copper and steel. Processor (die) temperatures are monitored using a custom script.


                                                                                                                                                                               3 stage experimental setup to isolate impact of PCM                                                                                                  
Computational Model

Device level model was made to evaluate thermal performance of PCMs integrated into realistic mobile devices. The heat dissipation paths with and without the PCMs were studied to assess the impact of PCM. The processor was modeled as a uniform block of Silicon. However, a typical processor package consists of multiple layers and has localized heat generating regions on the die (hotspots). For example, the silicon die is typically attached to the substrate by solder bumps and interconnects encapsulated in an epoxy. Hence model refinements were done at the processor level and various die floorplans were studied. Comsol was used for thermal modeling. 

                                                                                                          Cross section of a mobile package for system                                 Schematic of model geometry in Comsol for studying
                                                                                        level simulations. Model is made from teardowns                                              the influence of PCM "on-chip"
                                                                                                                    publicly available

  • Comparison of thermal performance of commercial PCMs using industry standard benchmarks such as LINPACK to stress the processor on the time taken to reach cutoff temperature for the processor. For certain enclosure (which houses the PCM) sizes, the addition of PCM increases the cutoff time by a factor of 2.48 relative to an unfilled enclosure of same height and width
  • Thermal characterization of select PCM thermophysical properties such as thermal conductivity and latent heat
  • Assessed impact of PCM properties on cutoff times using system and package level thermal models