On-going Projects
  • Neural network based link adaptation algorithm and its on-chip network architecture: National Research Foundation of Korea (NRF) (06/2017 ~ 05/2020)
The selection of Modulation and Coding Scheme (MCS) that suit the given channel condition best, the so-called link adaptation, is a key element of high throughput communication networks such as 4G LTE and WiFi in that its performance (e.g., goodput or energy efficiency) heavily depends on how link adaptation is carried out. In this project, we firstly develop the neural network based link adaptation algorithm and its on-chip network for the system-on-chip implementation. Firstly, the architecture and parameters of the neural network are derived based on the simulation results, a training method with self-generated training data is newly proposed, and the throughput is measured over the air. Secondly, based on the design space exploration using the transaction-level model simulator, the topology and protocol of the on-chip network for the neural network are optimized in terms of processing speed and power consumption. Also the architecture of the hardware accelerator capable of parallel processing is designed. Lastly, the proposed algorithm and on-chip network are optimized further and verified using the proprietary prototype system consisting of modem and neural network.

    • SW-oriented university education program: Institute for Information & Communications Technology Promotion (IITP) (03/2018 ~ 02/2022)
    The design space exploration is crucial to the design of embedded systems in terms of performance and complexity. In this project, we focus on the design space exploration of hardware accelerator for various emerging technologies, e.g., deep neural networks. In particular, the dataflow of the hardware accelerator, which characterizes the memory access and interconnect usage, is optimized using the open-source software programs such as Aladdin, gem5 etc. The optimized design is verified based on the implementation using the commerically available SoC platforms such as Xilinx's ZYNQ. The students who participate in this program will be closely advised by academia and industry.
    • Intelligent system LSI for wireless communications: Korea Institute for Advancement of Technology (KIAT) (03/2016 ~ 02/2021)
    The design of a system-on-chip (SoC) for digital signal processing applications heavily relies on a few design decisions such as hardware-software partitioning and on-chip network optimization. In this project, we newly develope an efficient design procedure where the aforementioned design decisions are carefully handled. The use of high-level design tools such as SystemC based transaction-level modeling (TLM) will be closely investigated. The design procedure devised in this project will be applied to the design of emerging technologies such as neural network platforms, compressed sensing and software-defined radios.
    • Dataflow exploration tool for deep neural networks (In preparation)

    Completed Projects
    • Reconfigurable multi-band channelizer based on compressed-sensing: National Research Foundation of Korea (NRF) (05/2014 ~ 04/2017)

      Blind wideband sampling is one of the break-through sub-sampling techniques that enables the sub-Nyquist sampling of a wideband sparse signal without knowing the frequency location of constituent narrowband signals. Blind wideband sampling consists of Modulated Wideband Converter (MWC) and reconfigurable multi-band channelier. The latter first estimates the frequency location of the constituent narrowband signals and then hand them over to the following functional block, e.g, digital baseband receiver. Compressed sensing has emerged as a promising signal processing algorithm since it has a broad range of applications in wireless communications (e.g., massive MIMO) and biomedical imaging (e.g., ultra-sound imaging). Academia has recently made a lot of research effort to devise efficient SoC architectures for compressed sensing. In this project, orthogonal matching pursuit (OMP), one of the well-known compressed sensing algorithm, is implemented on commercially available FPGA (Xilinx ZYNQ 7020). The focus is given to the design space exploration for the hardware-software partitioning and on-chip communication architectures, which is facilitated by the use of transaction level model (TLM) based on the so-called communication analysis graph (CAG).

    • Digital FrontEnd (DFE) design for 2/3/4G cellular networks: LG Electronics (04/2014 ~ 03/2016)
    Digital FrontEnd (DFE) resides between RF/analog transceiver and digital baseband modem. In more detail, its transmitter part follows the digital baseband transmitter and precedes the Digital-to-Analog Converter (DAC), whereas its receiver part follows the Analog-to-Digital Converter (ADC) and precedes the digital baseband receiver. The major roles of DFE include channel selection, sample rate conversion and impairment compensation. Digital up/down conversion may be used to support multi-carrier transmission/reception such as multi-carrier WCDMA and carrier aggregation (LTE-Advanced). It should be noted that DFE involes prohibitively high computational complexity and its operating frequency is generally much higher than that of digital baseband modem. Many sophisticated signal processing algorithms and architectures are useful to the successful implementation of DFE, for example, polynomial interpolation (e.g., Farrow interpolation), reconfigurable digital FIR filtering (e.g., Constant Shift Method (CSM)), COordinate Rotation DIgital Computer (CORDIC).

      • Advanced link adaptation engine for WiFi: LG Electronics (04/2015 ~ 09/2015)
      The selection of Modulation and Coding Scheme (MCS) that suit the given channel condition best, the so-called link adaptation, is a key element of a WiFi PHY/MAC system in that its performance (e.g., goodput or energy efficiency) heavily depends on how link adaptation is carried out. It is largely categorized into two approaches: ACK-based approach and preamble-based approach. ACK-based approach (e.g., Automatic Rate Fallback (ARF) from Lucent Bell Lab.) simply counts the number of successive successes/failures of data transmissions and increases/decreases the MCS accordingly, whereas preamble-based approach (e.g., Exponential effective SNR mapping (EESM) from Ericsson) measures the SNR based on the received preamble and maps it into the throughput-maximizing MCS.

      • Reconfiguralbe mult-band OFDMA architecture: Konkuk University (05/2014 ~ 04/2015)
      • Algorithms and SoC (System-on-a-Chip) architectures for advanced signal processing: Konkuk University (04/2013 ~ 03/2014)