Jeongpil Park (박정필)









Silicon Works, LG Electronics (2017~) 
Research Interest : System-on-a-Chip design for signal processing
 
Educations
B.S. in Electrical Engineering, Konkuk University, Seoul, Korea, 02/2015
M.S. in Electrical Engineering, Konkuk University, Seoul, Korea, 02/2017
 - Thesis: System-on-chip design and implementation of digital front-end for multimode mobile communication terminals

Projects
Digital FrontEnd (DFE) design for 2/3/4G cellular networks: LG Electronics (03/2015 ~ 03/2016)
 - System design of multimode digital front-end: fractional sampling, channel selection filtering, digital compensation
 - RTL implementation of multimode digital front-end ASIC
 - SoC implementation of IQ imbalance compensation (Xilinx ZYNQ)
Advanced link adaptation engine for WiFi: LG Electronics (04/2015 ~ 09/2015)
 - F/W implementation for auto-rate fallback (ARF)
 - F/W implementation for adaptive preamble-based link adaptation (APBLA)

Honor and Awards

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