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Term Project (revision2)

posted Nov 21, 2017, 4:24 AM by Chester Sungchung Park   [ updated ]

Assignment #2

posted Nov 13, 2017, 4:56 PM by Chester Sungchung Park   [ updated Nov 21, 2017, 4:23 AM ]

Team report about Lab 3-1 & 3-2 that must include:

- Summary of Lab 3 [10pt]
- Demo results (screenshot etc.) [10pt]
- C source code analysis (flow chart etc.) [15pt]
- Verilog HDL source code analysis (block diagram etc.) [15pt]

The purpose of this assignment is to help students to understand the source codes.

Due date: Nov. 24, 2017, 23:59:59 GMT+9 (no delay allowed)
Zip the following files into a single file and send it to chesterku2013@gmail.com (Note: one zip file per team)
- Team report
- Modified C source codes
- Modified Verilog HDL source codes

Assignment #1

posted Sep 23, 2017, 9:08 PM by Chester Sungchung Park   [ updated Sep 28, 2017, 5:37 AM by Sunwoo Kim ]

Please check the assignment in the link below (Revision 2):

Please download the relevent files (FixedDT library, template codes, input files) in the link below (Revision 1):

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